Inventor · disambiguated record
Conor P. Puls
Also filed as: PULS CONOR · PULS CONOR P
6 granted patents·26 pending applications·15 citations·filing 2018–2025
74Inventor score
Top patents by PatentIndex Score
32 records- 0195US11239238B2Thin film transistor based memory cells on both sides of a layer of logic devicesINTEL CORP·Filed 2019·Granted Feb 1, 2022·13 cites·23 claims
- 0284US12014996B2Moisture hermetic guard ring for semiconductor on insulator devicesINTEL CORP·Filed 2020·Granted Jun 18, 2024·2 cites·12 claims
- 0374US12406945B2Moisture hermetic guard ring for semiconductor on insulator devicesINTEL CORP·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 0470US2025323127A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2025·Application pending·0 cites
- 0569US11690211B2Thin film transistor based memory cells on both sides of a layer of logic devicesINTEL CORP·Filed 2021·Granted Jun 27, 2023·0 cites·19 claims
- 0669US2025324697A1Mitigating proximity effects of deep trench viasINTEL CORP·Filed 2025·Application pending·0 cites
- 0768US2025227968A1Integrated circuit structure with backside power deliveryINTEL CORP·Filed 2025·Application pending·0 cites
- 0868US2024332301A1Integrated circuit structures with sub-fin isolationINTEL CORP·Filed 2023·Application pending·0 cites
- 0967US12469780B2Integrated circuit structure with recessed self-aligned deep boundary viaINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·20 claims
- 1065US2025112120A1Integrated circuit structure with deep via bar width tuningINTEL CORP·Filed 2023·Application pending·0 cites
- 1164US2025227993A1Integrated circuit structures with sub-fin isolationINTEL CORP·Filed 2025·Application pending·0 cites
- 1261US2023197779A1Integrated circuit structure with backside power deliveryINTEL CORP·Filed 2021·Application pending·0 cites
- 1361US2025098249A1Mitigating proximity effects of deep trench viasINTEL CORP·Filed 2023·Application pending·0 cites
- 1457US2022393013A1Fabrication of gate-all-around integrated circuit structures having pre-spacer-deposition wide cut gatesINTEL CORP·Filed 2021·Application pending·0 cites
- 1556US2025267909A1Integrated circuit structure with direct backside source or drain contact enabled by silicon germanium etch stopINTEL CORP·Filed 2024·Application pending·0 cites
- 1656US2025140748A1Double-sided conductive viaINTEL CORP·Filed 2023·Application pending·0 cites
- 1755US2025142948A1Integrated circuit devices with self-aligned via-to-jumper connectionsINTEL CORP·Filed 2023·Application pending·0 cites
- 1854US2025096114A1Via structure with improved substrate groundingINTEL CORP·Filed 2023·Application pending·0 cites
- 1953US2025220991A1Integrated circuit structure with direct backside source or drain contactINTEL CORP·Filed 2023·Application pending·0 cites
- 2052US2025105095A1Integrated circuit devices with vias having widened ends for power deliveryINTEL CORP·Filed 2023·Application pending·0 cites
- 2151US2025006547A1Integrated circuit structures with removed sub-finINTEL CORP·Filed 2023·Application pending·0 cites
- 2251US2025029892A1Integrated circuit structures having through-stack thermal sink for dual-sided devicesINTEL CORP·Filed 2023·Application pending·0 cites
- 2350US2025132245A1Electrically self-insulated viaINTEL CORP·Filed 2023·Application pending·0 cites
- 2450US2022415892A1Stacked two-level backend memoryINTEL CORP·Filed 2021·Application pending·0 cites
- 2548US2022399334A1Integrated circuit structures with backside self-aligned conductive via barINTEL CORP·Filed 2021·Application pending·0 cites
- 2648US2025006579A1Mitigation of threshold voltage shift in backside power delivery using backside passivation layerINTEL CORP·Filed 2023·Application pending·0 cites
- 2748US2024222447A1Gate cut, and source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 2847US2022399445A1Conductive via bar self-aligned to gate endINTEL CORP·Filed 2021·Application pending·0 cites
- 2947US2023197538A1Hermetic seal for transistors with metal on both sidesINTEL CORP·Filed 2021·Application pending·0 cites
- 3046US11380838B2Magnetic memory devices with layered electrodes and methods of fabricationINTEL CORP·Filed 2018·Granted Jul 5, 2022·0 cites·22 claims
- 3146US2023317563A1Vias with vertically non-uniform or discontinuous stackINTEL CORP·Filed 2022·Application pending·0 cites
- 3245US2023317594A1Device performance tuning by deep trench via (dvb) proximity effect in architecture of backside power deliveryCHU TAO·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →