Mitigation of threshold voltage shift in backside power delivery using backside passivation layer

Abstract

Devices, transistor structures, systems, and techniques are described herein related to providing a backside passivation layer on a transistor semiconductor material. The semiconductor material is between source and drain structures, and a gate structure is adjacent a channel region of the semiconductor material. The passivation layer is formed as a conformal insulative layer on a backside of the semiconductor material and is then treated using an ozone/UV cure to remove trap charges from the semiconductor material.

What is claimed is: 
     
         1 . An apparatus, comprising:
 a transistor comprising a semiconductor structure extending between a source structure and a drain structure, and a gate structure over a channel region of the semiconductor structure;   a via extending from a frontside metallization over the transistor to a backside metallization below the transistor;   a first insulative layer on a backside of the semiconductor structure; and   a second insulative layer on the first insulative layer.   
     
     
         2 . The apparatus of  claim 1 , wherein the first insulative layer comprises one or more of silicon, carbon, oxygen, and nitrogen. 
     
     
         3 . The apparatus of  claim 1 , wherein the first insulative layer comprises silicon and nitrogen or aluminum and oxygen. 
     
     
         4 . The apparatus of  claim 1 , wherein the first insulative layer comprises silicon and nitrogen and the second insulative layer comprises silicon and oxygen, wherein the first insulative layer has a thickness of not more than 10 nm. 
     
     
         5 . The apparatus of  claim 4 , wherein the semiconductor structure has a thickness between the backside of the semiconductor structure and a frontside of the semiconductor structure of not more than 100 nm. 
     
     
         6 . The apparatus of  claim 1 , further comprising an insulative liner adjacent the via, wherein a portion of the first insulative layer is on a sidewall of the insulative liner. 
     
     
         7 . The apparatus of  claim 6 , wherein a bottom surface of the second insulative layer is substantially coplanar with a bottom surface of the via. 
     
     
         8 . The apparatus of  claim 1 , wherein the gate structure is on a first portion of the semiconductor structure, a third insulative layer is on a second portion of the semiconductor structure, and the gate structure is on the third insulative layer, and wherein a bottom surface of the third insulative layer is substantially coplanar with a bottom surface of the semiconductor structure and the first insulative layer is on the bottom surface of the third insulative layer. 
     
     
         9 . The apparatus of  claim 1 , wherein the backside metallization comprises a power delivery metallization feature in contact with the via. 
     
     
         10 . A system, comprising:
 an integrated circuit (IC) die comprising:
 a transistor comprising a semiconductor structure extending between a source and a drain, and a gate on a frontside of the semiconductor structure; 
 a bridge via extending from a frontside metal over the transistor to a backside metal below the transistor; 
 a conformal insulative layer on a backside of the semiconductor structure; and 
 an insulative fill layer on the conformal insulative layer; and 
   a power supply coupled to the IC die.   
     
     
         11 . The system of  claim 10 , wherein the conformal insulative layer comprises silicon and nitrogen and the insulative fill layer comprises silicon and oxygen, wherein the conformal insulative layer has a thickness of not more than 10 nm. 
     
     
         12 . The system of  claim 11 , wherein the semiconductor structure has a thickness between the frontside of the semiconductor structure and the backside of the semiconductor structure of not more than 100 nm. 
     
     
         13 . The system of  claim 10 , further comprising an insulative liner adjacent the bridge via, wherein a portion of the conformal insulative layer is on a sidewall of the insulative liner, and a bottom surface of the insulative fill layer is substantially coplanar with a bottom surface of the bridge via. 
     
     
         14 . The system of  claim 10 , wherein the gate is on a first portion of the semiconductor structure, a second insulative fill layer is on a second portion of the semiconductor structure, and the gate is on the second insulative fill layer, and wherein a bottom surface of the second insulative fill layer is substantially coplanar with a bottom surface of the semiconductor structure and the conformal insulative layer is on the bottom surface of the second insulative fill layer. 
     
     
         15 . A method, comprising:
 exposing a backside of a semiconductor structure, wherein the semiconductor structure extends between a source structure and a drain structure, and a gate structure is couple to the semiconductor structure;   etching at least a portion of the semiconductor structure via the exposed backside of the semiconductor structure to form a surface of the semiconductor structure;   forming a first insulative layer on the surface of the semiconductor structure;   performing an ozone and ultraviolet anneal of the first insulative layer; and   forming a second insulative layer over the first insulative layer.   
     
     
         16 . The method of  claim 15 , wherein the first insulative layer comprises one or more of silicon, carbon, oxygen, and nitrogen. 
     
     
         17 . The method of  claim 15 , wherein the first insulative layer comprises silicon and nitrogen and the second insulative layer comprises silicon and oxygen, wherein the first insulative layer has a thickness of not more than 10 nm. 
     
     
         18 . The method of  claim 17 , wherein the first insulative layer has a thickness of not more than 5 nm. 
     
     
         19 . The method of  claim 15 , wherein a via extends from a frontside metallization over the semiconductor structure to a backside surface of the via, and wherein etching at least the portion of the semiconductor structure provides an etch back of the semiconductor structure such that the backside surface of the via is below the surface of the semiconductor structure. 
     
     
         20 . The method of  claim 19 , wherein forming the first insulative layer on the surface of the semiconductor structure further forms the first insulative layer on a sidewall of an insulative liner adjacent the via.