Inventor · disambiguated record
David Abercrombie
Also filed as: ABERCROMBIE DAVID · ABERCROMBIE DAVID A
22 granted patents·2 pending applications·469 citations·filing 1996–2019
95Inventor score
Top patents by PatentIndex Score
24 records- 0194US6807655B1Adaptive off tester screening method based on intrinsic die parametric measurementsLSI LOGIC CORP·Filed 2002·Granted Oct 19, 2004·107 cites·18 claims
- 0293US5666063AMethod and apparatus for testing an integrated circuitMOTOROLA INC·Filed 1996·Granted Sep 9, 1997·121 cites·49 claims
- 0391US7460211B2Apparatus for wafer patterning to reduce edge exclusion zoneLSI CORP·Filed 2006·Granted Dec 2, 2008·16 cites·8 claims
- 0483US8612919B2Model-based design verificationPIKUS FEDOR G·Filed 2007·Granted Dec 17, 2013·14 cites·16 claims
- 0581US7725849B2Feature failure correlationMENTOR GRAPHICS CORP·Filed 2005·Granted May 25, 2010·12 cites·50 claims
- 0681US5937324AMethod for forming a line-on-line multi-level metal interconnect structure for use in integrated circuitsMOTOROLA INC·Filed 1998·Granted Aug 10, 1999·67 cites·20 claims
- 0776US7062415B2Parametric outlier detectionLSI LOGIC CORP·Filed 2004·Granted Jun 13, 2006·22 cites·20 claims
- 0876US6980917B2Optimization of die yield in a silicon wafer “sweet spot”LSI LOGIC CORP·Filed 2002·Granted Dec 27, 2005·17 cites·13 claims
- 0976US5798568ASemiconductor component with multi-level interconnect system and method of manufactureMOTOROLA INC·Filed 1996·Granted Aug 25, 1998·50 cites·22 claims
- 1072US7174281B2Method for analyzing manufacturing dataLSI LOGIC CORP·Filed 2002·Granted Feb 6, 2007·7 cites·8 claims
- 1166US7039556B2Substrate profile analysisLSI LOGIC CORP·Filed 2004·Granted May 2, 2006·12 cites·18 claims
- 1265US7390680B2Method to selectively identify reliability risk die based on characteristics of local regions on the waferLSI CORP·Filed 2005·Granted Jun 24, 2008·2 cites·10 claims
- 1362US9652574B2Simultaneous multi-layer fill generationANIKIN EUGENE·Filed 2011·Granted May 16, 2017·2 cites·8 claims
- 1462US7454387B2Method of isolating sources of variance in parametric dataLSI CORP·Filed 2003·Granted Nov 18, 2008·12 cites·14 claims
- 1554US10552565B2Simultaneous multi-layer fill generationMENTOR GRAPHICS CORP·Filed 2016·Granted Feb 4, 2020·0 cites·20 claims
- 1649US7930655B2Yield profile manipulatorLSI CORP·Filed 2008·Granted Apr 19, 2011·0 cites·8 claims
- 1748US7137098B2Pattern component analysis and manipulationLSI LOGIC CORP·Filed 2004·Granted Nov 14, 2006·3 cites·20 claims
- 1848US6880140B2Method to selectively identify reliability risk die based on characteristics of local regions on the waferLSI LOGIC CORP·Filed 2003·Granted Apr 12, 2005·2 cites·9 claims
- 1945US6658361B1Heaviest only fail potentialLSI LOGIC CORP·Filed 2001·Granted Dec 2, 2003·3 cites·20 claims
- 2045US2009077506A1Simultaneous Multi-Layer Fill GenerationANIKIN EUGENE·Filed 2008·Application pending·0 cites
- 2143US12032892B2Semiconductor layout context around a point of interestSIEMENS IND SOFTWARE INC·Filed 2019·Granted Jul 9, 2024·0 cites·20 claims
- 2243US7395522B2Yield profile manipulatorLSI CORP·Filed 2004·Granted Jul 1, 2008·0 cites·12 claims
- 2342US2008034332A1Optimization Of Geometry Pattern DensityMENTOR GRAPHICS CORP·Filed 2007·Application pending·0 cites
- 2438US7653523B2Method for calculating high-resolution wafer parameter profilesLSI CORP·Filed 2003·Granted Jan 26, 2010·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →