Inventor · disambiguated record
Daniel Jaeger
Also filed as: JAEGER DANIEL · JAEGER DANIEL J
35 granted patents·7 pending applications·127 citations·filing 2009–2019
96Inventor score
Top patents by PatentIndex Score
42 records- 0195US10325819B1Methods, apparatus and system for providing a pre-RMG replacement metal contact for a finFET deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 18, 2019·15 cites·20 claims
- 0293US10373875B1Contacts formed with self-aligned cutsGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 6, 2019·7 cites·9 claims
- 0393US10269654B1Methods, apparatus and system for replacement contact for a finFET deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Apr 23, 2019·12 cites·20 claims
- 0493US9761452B1Devices and methods of forming SADP on SRAM and SAQP on logicGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·7 cites·15 claims
- 0592US8053301B2CMOS SiGe channel pFET and Si channel nFET devices with minimal STI recessIBM·Filed 2009·Granted Nov 8, 2011·27 cites·14 claims
- 0689US9035430B2Semiconductor fin on local oxideVEGA REINALDO A·Filed 2012·Granted May 19, 2015·9 cites·19 claims
- 0786US10644156B2Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted May 5, 2020·5 cites·12 claims
- 0886US8129234B2Method of forming bipolar transistor integrated with metal gate CMOS devicesWALLNER THOMAS A·Filed 2009·Granted Mar 6, 2012·14 cites·12 claims
- 0985US9589829B1FinFET device including silicon oxycarbon isolation structureGLOBALFOUNDRIES INC·Filed 2015·Granted Mar 7, 2017·4 cites·20 claims
- 1083US9299795B2Partial sacrificial dummy gate with CMOS device with high-k metal gateIBM·Filed 2015·Granted Mar 29, 2016·3 cites·4 claims
- 1182US10340142B1Methods, apparatus and system for self-aligned metal hard masksGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 2, 2019·3 cites·17 claims
- 1281US9041076B2Partial sacrificial dummy gate with CMOS device with high-k metal gateIBM·Filed 2013·Granted May 26, 2015·4 cites·16 claims
- 1380US10833160B1Field-effect transistors with self-aligned and non-self-aligned contact openingsGLOBALFOUNDRIES INC·Filed 2019·Granted Nov 10, 2020·3 cites·9 claims
- 1480US10418455B2Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 17, 2019·2 cites·9 claims
- 1577US10991796B2Source/drain contact depth controlGLOBALFOUNDRIES US INC·Filed 2018·Granted Apr 27, 2021·2 cites·10 claims
- 1677US10204797B1Methods, apparatus, and system for reducing step height difference in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 12, 2019·2 cites·20 claims
- 1776US9780002B1Threshold voltage and well implantation method for semiconductor devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·2 cites·20 claims
- 1876US9711624B1Methods for direct measurement of pitch-walking in lithographic multiple patterningGLOBALFOUNDRIES INC·Filed 2016·Granted Jul 18, 2017·2 cites·20 claims
- 1967US8415212B2Method of enhancing photoresist adhesion to rare earth oxidesSCHAEFFER JAMES K·Filed 2010·Granted Apr 9, 2013·3 cites·20 claims
- 2061US8629028B2Metal oxide semiconductor field effect transistor (MOSFET) gate terminationIBM·Filed 2013·Granted Jan 14, 2014·1 cites·17 claims
- 2160US10930549B2Cap structureGLOBALFOUNDRIES INC·Filed 2019·Granted Feb 23, 2021·0 cites·15 claims
- 2259US10522639B2Methods, apparatus and system for stringer defect reduction in a trench cut region of a finFET deviceGLOBALFOUNDRIES INC·Filed 2019·Granted Dec 31, 2019·0 cites·12 claims
- 2356US10460986B2Cap structureGLOBALFOUNDRIES INC·Filed 2018·Granted Oct 29, 2019·0 cites·20 claims
- 2456US9853116B2Partial sacrificial dummy gate with CMOS device with high-k metal gateIBM·Filed 2015·Granted Dec 26, 2017·0 cites·9 claims
- 2556US2019295898A1Contacts formed with self-aligned cutsGLOBALFOUNDRIES INC·Filed 2019·Application pending·0 cites
- 2654US2015044843A1Semiconductor fin on local oxideIBM·Filed 2014·Application pending·0 cites
- 2751US2018012760A1Devices and methods of forming sadp on sram and saqp on logicGLOBALFOUNDRIES INC·Filed 2017·Application pending·0 cites
- 2850US11907685B2Structure and method for random code generationGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 20, 2024·0 cites·20 claims
- 2950US2013140670A1Structure and method for reduction of vt-w effect in high-k metal gate devicesIBM·Filed 2013·Application pending·0 cites
- 3048US10971625B2Epitaxial structures of a semiconductor device having a wide gate pitchGLOBALFOUNDRIES US INC·Filed 2019·Granted Apr 6, 2021·0 cites·18 claims
- 3147US11056398B2Forming interconnect without gate cut isolation blocking opening formationGLOBALFOUNDRIES US INC·Filed 2019·Granted Jul 6, 2021·0 cites·12 claims
- 3246US8569840B2Bipolar transistor integrated with metal gate CMOS devicesWALLNER THOMAS A·Filed 2012·Granted Oct 29, 2013·0 cites·20 claims
- 3344US10755982B1Methods of forming gate structures for transistor devices on an IC productGLOBALFOUNDRIES INC·Filed 2019·Granted Aug 25, 2020·0 cites·19 claims
- 3444US10388562B2Composite contact etch stop layerGLOBALFOUNDRIES INC·Filed 2017·Granted Aug 20, 2019·0 cites·18 claims
- 3544US2012187522A1Structure and method for reduction of vt-w effect in high-k metal gate devicesAQUILINO MICHAEL V·Filed 2011·Application pending·0 cites
- 3642US10714376B2Method of forming semiconductor material in trenches having different widths, and related structuresGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 14, 2020·0 cites·14 claims
- 3742US2011132353A1Transportable multi-configurable self-ballasted modular solar power unitSUNPOD S INC·Filed 2010·Application pending·0 cites
- 3841US10249616B2Methods of forming a resistor structure between adjacent transistor gates on an integrated circuit product and the resulting devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 2, 2019·0 cites·16 claims
- 3941US8859388B2Sealed shallow trench isolation regionAQUILINO MICHAEL V·Filed 2012·Granted Oct 14, 2014·0 cites·13 claims
- 4041US8704332B2Metal oxide semiconductor field effect transistor (MOSFET) gate terminationBAIOCCO CHRISTOPHER V·Filed 2012·Granted Apr 22, 2014·0 cites·10 claims
- 4141US2013145327A1Interfaces for Displaying an Intersection SpaceRINEARSON PETER·Filed 2012·Application pending·0 cites
- 4238US10062612B2Method and system for constructing FINFET devices having a super steep retrograde wellGLOBALFOUNDRIES INC·Filed 2016·Granted Aug 28, 2018·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Daniel Jaeger files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →