Inventor · disambiguated record
David J. Krolak
Also filed as: KROLAK DAVID · KROLAK DAVID J · KROLAK DAVID JOHN
42 granted patents·5 pending applications·554 citations·filing 1988–2023
97Inventor score
Top patents by PatentIndex Score
47 records- 0191US11580058B1Hierarchical ring-based interconnection network for symmetric multiprocessorsIBM·Filed 2021·Granted Feb 14, 2023·2 cites·25 claims
- 0291US4888773ASmart memory card architecture and interfaceIBM·Filed 1988·Granted Dec 19, 1989·198 cites·11 claims
- 0389US7302510B2Fair hierarchical arbiterIBM·Filed 2005·Granted Nov 27, 2007·22 cites·20 claims
- 0488US10216653B2Pre-transmission data reordering for a serial interfaceIBM·Filed 2017·Granted Feb 26, 2019·5 cites·19 claims
- 0588US7500035B2Livelock resolution methodIBM·Filed 2006·Granted Mar 3, 2009·16 cites·20 claims
- 0687US6138209AData processing system and multi-way set associative cache utilizing class predict data structure and method thereofIBM·Filed 1997·Granted Oct 24, 2000·146 cites·47 claims
- 0783US9626229B1Processor performance monitoring unit synchronizationIBM·Filed 2016·Granted Apr 18, 2017·4 cites·20 claims
- 0879US7669013B2Directory for multi-node coherent busIBM·Filed 2007·Granted Feb 23, 2010·9 cites·20 claims
- 0974US9495314B2Determining command rate based on dropped commandsIBM·Filed 2014·Granted Nov 15, 2016·2 cites·7 claims
- 1074US9495312B2Determining command rate based on dropped commandsIBM·Filed 2013·Granted Nov 15, 2016·2 cites·15 claims
- 1173US10606777B2Dropped command truncation for efficient queue utilization in multiprocessor data processing systemIBM·Filed 2018·Granted Mar 31, 2020·1 cites·20 claims
- 1270US5790838APipelined memory interface and method for using the sameIBM·Filed 1996·Granted Aug 4, 1998·30 cites·19 claims
- 1369US12099463B2Hierarchical ring-based interconnection network for symmetric multiprocessorsIBM·Filed 2022·Granted Sep 24, 2024·0 cites·10 claims
- 1468US6151664AProgrammable SRAM and DRAM cache interface with preset access prioritiesIBM·Filed 1999·Granted Nov 21, 2000·50 cites·26 claims
- 1567US5751990AAbridged virtual address cache directoryIBM·Filed 1994·Granted May 12, 1998·48 cites·18 claims
- 1665US9251111B2Command rate configuration in data processing systemIBM·Filed 2013·Granted Feb 2, 2016·1 cites·13 claims
- 1765US8171448B2Structure for a livelock resolution circuitJOHNS CHARLES R·Filed 2008·Granted May 1, 2012·3 cites·18 claims
- 1863US12095891B2Communication systems for power supply noise reductionIBM·Filed 2022·Granted Sep 17, 2024·0 cites·18 claims
- 1961US12176960B2Communication systems for power supply noise reductionIBM·Filed 2022·Granted Dec 24, 2024·0 cites·18 claims
- 2060US8510512B2Memory coherence directory supporting remotely sourced requests of nodal scopeGANFIELD PAUL A·Filed 2009·Granted Aug 13, 2013·2 cites·11 claims
- 2159US7725660B2Directory for multi-node coherent busIBM·Filed 2007·Granted May 25, 2010·1 cites·20 claims
- 2258US9324031B2System interconnect dynamic scaling by predicting I/O requirementsIBM·Filed 2014·Granted Apr 26, 2016·1 cites·11 claims
- 2358US9324030B2System interconnect dynamic scaling by predicting I/O requirementsIBM·Filed 2014·Granted Apr 26, 2016·1 cites·18 claims
- 2458US2024348217A1Asymmetric operational amplifierSEMICONDUCTOR COMPONENTS IND LLC·Filed 2023·Application pending·0 cites
- 2557US9575921B2Command rate configuration in data processing systemIBM·Filed 2014·Granted Feb 21, 2017·0 cites·7 claims
- 2655US10693595B2ACK clock compensation for high-speed serial communication interfacesIBM·Filed 2018·Granted Jun 23, 2020·0 cites·9 claims
- 2755US7861022B2Livelock resolutionIBM·Filed 2009·Granted Dec 28, 2010·0 cites·20 claims
- 2853US10664398B2Link-level cyclic redundancy check replay for non-blocking coherence flowIBM·Filed 2018·Granted May 26, 2020·0 cites·20 claims
- 2952US8112590B2Methods and apparatus for reducing command processing latency while maintaining coherenceBROWN JEFFREY DOUGLAS·Filed 2007·Granted Feb 7, 2012·0 cites·22 claims
- 3052US7797600B2Method and apparatus for testing a ring of non-scan latches with logic built-in self-testIBM·Filed 2008·Granted Sep 14, 2010·1 cites·14 claims
- 3152US7406640B2Method and apparatus for testing a ring of non-scan latches with logic built-in self-testIBM·Filed 2006·Granted Jul 29, 2008·1 cites·6 claims
- 3250US10128985B2ACK clock compensation for high-speed serial communication interfacesIBM·Filed 2016·Granted Nov 13, 2018·0 cites·14 claims
- 3349US10969822B2Reducing time of day latency variation in a multi processor systemIBM·Filed 2019·Granted Apr 6, 2021·0 cites·18 claims
- 3449US2007186052A1Methods and apparatus for reducing command processing latency while maintaining coherenceIBM·Filed 2006·Application pending·0 cites
- 3548US8504779B2Memory coherence directory supporting remotely sourced requests of nodal scopeGANFIELD PAUL A·Filed 2012·Granted Aug 6, 2013·0 cites·6 claims
- 3647US11341060B2Multifunction communication interface supporting memory sharing among data processing systemsIBM·Filed 2020·Granted May 24, 2022·0 cites·22 claims
- 3746US10613980B2Coherence protocol providing speculative coherence response to directory probeIBM·Filed 2017·Granted Apr 7, 2020·0 cites·18 claims
- 3844US10324491B2Reducing time of day latency variation in a multi-processor systemIBM·Filed 2017·Granted Jun 18, 2019·0 cites·18 claims
- 3944US2007174556A1Methods and apparatus for reducing command reissue latencyIBM·Filed 2006·Application pending·0 cites
- 4044US2007186027A1Method and apparatus for implementing control of a multiple ring hybrid crossbar partially non-blocking data switchIBM·Filed 2006·Application pending·0 cites
- 4143US7487267B2Method and apparatus for managing dependencies between split transaction queuesIBM·Filed 2006·Granted Feb 3, 2009·0 cites·3 claims
- 4243US7124257B2Bus interface controller for determining access countsIBM·Filed 2002·Granted Oct 17, 2006·0 cites·25 claims
- 4342US2006206657A1Single port/multiple ring implementation of a hybrid crossbar partially non-blocking data switchCLARK SCOTT D·Filed 2005·Application pending·0 cites
- 4436US6198316B1CMOS off-chip driver circuitIBM·Filed 1999·Granted Mar 6, 2001·4 cites·12 claims
- 4530US6523080B1Shared bus non-sequential data ordering method and apparatusIBM·Filed 1998·Granted Feb 18, 2003·2 cites·6 claims
- 4629US5748919AShared bus non-sequential data ordering method and apparatusIBM·Filed 1996·Granted May 5, 1998·1 cites·3 claims
- 4728US5649177AControl logic for very fast clock speedsIBM·Filed 1995·Granted Jul 15, 1997·1 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →