Pipelined memory interface and method for using the same

Abstract

According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for the CPU is also used to generate the clock signals for all of the other components that interface with the SRAM. Each of the generated clock signals are dependant on the same clock event, allowing the clock speed to be decreased for testing or debugging while maintaining higher speed clock edge relationships. The various clock signals that are generated from the oscillator are used to cycle-steal time from multiple cycles. This technique allows sub-5 nanosecond (nS) access to Level 2 and Level 3 cache memory devices that have access times greater than 5 nS.

We claim: 
     
       1. A memory interface for a memory device, the memory interface comprising: a data capture clock generation circuit, the data capture clock generation circuit generating at least one data capture clock signal coupled to the memory device;   a processor clock generation circuit, the processor clock generation circuit generating an address clock signal coupled to the memory device;   a memory clock generation circuit, the memory clock generation circuit generating at least one memory clock signal, the at least one memory clock signal latching in the address to the memory device and latching data out from the memory device; and   a master clock signal, the master clock signal providing a clock event which is used to generate the data capture clock signal, the address clock signal, and the memory clock signal.   
     
     
       2. The memory interface of claim 1 wherein the memory device is a level 2 SRAM cache. 
     
     
       3. The memory interface of claim 1 wherein the memory device is a level 3 SRAM cache. 
     
     
       4. A computer-implemented method of accessing an external component, the method comprising the steps of: providing an external component;   providing a capture register;   generating a master clock signal;   generating from the same event of the master clock signal: an external component clock signal;   an address clock signal; and   a data capture clock signal;     accessing the external component by supplying the external component clock signal and the address clock to the external component, and supplying the capture clock signal to the capture register.   
     
     
       5. The method of claim 4, further comprising the steps of: providing a main oscillator signal;   using the main oscillator signal to generate the master clock signal.   
     
     
       6. The method of claim 4 wherein the external memory component is an SRAM memory device. 
     
     
       7. The method of claim 6 wherein the SRAM memory device further comprises a level 2 cache. 
     
     
       8. The method of claim 6 wherein the SRAM memory device further comprises a level 3 cache. 
     
     
       9. The method of claim 4 wherein the method uses cycle-stealing to access the external component. 
     
     
       10. A method of accessing an external memory device, the method comprising the steps of: providing a microprocessor, the microprocessor having a plurality of internal latches;   providing a data capture register;   providing the external memory device;   inputting a first clock signal into the microprocessor;   generating a second clock signal, a third clock signal, and a fourth clock signal from a single first clock signal event;   supplying the second clock signal to the internal latches of the microprocessor to latch addresses into the external memory device;   supplying the third clock signal to the external memory device to latch data from the external memory device;   supplying the fourth clock signal to the data capture register, so that the data capture register captures the data from the external memory device wherein the leading edge of the third clock signal arrives at the external memory device relative to the leading edge of the second clock signal arriving at the internal latches of the microprocessor and the leading edge of the fourth clock signal corresponds to a valid capture window for the external memory device.   
     
     
       11. The method of claim 10 wherein the external memory device is a level 2 SRAM cache. 
     
     
       12. The method of claim 10 wherein the external memory device is a level 3 SRAM cache. 
     
     
       13. The method of claim 10 wherein the fourth clock signal is programmable. 
     
     
       14. The method of claim 10 wherein the method uses cycle-stealing to access the external memory device. 
     
     
       15. An interface apparatus for at least one external component, the interface apparatus comprising: a clock input for generating a first clock signal and a second clock signal from a single event of the clock input;   at least one latch clocked by the first clock signal to capture data from the external component;   the second clock signal being supplied to the external component such that the external component operates at any frequency up to the maximum operating frequency of the external component.   
     
     
       16. The interface apparatus of claim 15 wherein the external component is an SRAM memory device. 
     
     
       17. The interface apparatus of claim 15 wherein the external component is a level 2 SRAM cache. 
     
     
       18. The interface apparatus of claim 15 wherein the external component is a level 3 SRAM cache. 
     
     
       19. The interface apparatus of claim 15 wherein the interface apparatus employs cycle-stealing to access the external component.