Inventor · disambiguated record
Sheldon B. Levenstein
Also filed as: LEVENSTEIN SHELDON · LEVENSTEIN SHELDON B · LEVENSTEIN SHELDON BERNARD
52 granted patents·4 pending applications·1,385 citations·filing 1989–2022
98Inventor score
Top patents by PatentIndex Score
56 records- 0197US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0297US6567839B1Thread switch control in a multithreaded processor systemIBM·Filed 1997·Granted May 20, 2003·424 cites·34 claims
- 0395US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0489US6105051AApparatus and method to guarantee forward progress in execution of threads in a multithreaded processorIBM·Filed 1997·Granted Aug 15, 2000·148 cites·14 claims
- 0587US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 0687US6138209AData processing system and multi-way set associative cache utilizing class predict data structure and method thereofIBM·Filed 1997·Granted Oct 24, 2000·146 cites·47 claims
- 0786US10078514B2Techniques for dynamic sequential instruction prefetchingIBM·Filed 2016·Granted Sep 18, 2018·4 cites·20 claims
- 0886US7809924B2System for generating effective addressIBM·Filed 2008·Granted Oct 5, 2010·15 cites·5 claims
- 0986US7350051B2Method to optimize effective page number to real page number translation path from page table entries match resumption of execution streamIBM·Filed 2005·Granted Mar 25, 2008·15 cites·6 claims
- 1086US7318127B2Method, apparatus, and computer program product for sharing data in a cache among threads in an SMT processorIBM·Filed 2005·Granted Jan 8, 2008·17 cites·14 claims
- 1185US7228385B2Processor, data processing system and method for synchronizing access to data in shared memoryIBM·Filed 2004·Granted Jun 5, 2007·39 cites·16 claims
- 1284US7284094B2Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence classIBM·Filed 2005·Granted Oct 16, 2007·14 cites·18 claims
- 1383US6088788ABackground completion of instruction and associated fetch request in a multithread processorIBM·Filed 1996·Granted Jul 11, 2000·123 cites·19 claims
- 1478US6205063B1Apparatus and method for efficiently correcting defects in memory circuitsIBM·Filed 1998·Granted Mar 20, 2001·38 cites·24 claims
- 1577US7571283B2Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatchIBM·Filed 2008·Granted Aug 4, 2009·7 cites·11 claims
- 1675US7200717B2Processor, data processing system and method for synchronizing access to data in shared memoryIBM·Filed 2004·Granted Apr 3, 2007·20 cites·20 claims
- 1773US10379857B2Dynamic sequential instruction prefetchingIBM·Filed 2018·Granted Aug 13, 2019·1 cites·20 claims
- 1873US7360058B2System and method for generating effective addressIBM·Filed 2005·Granted Apr 15, 2008·6 cites·3 claims
- 1972US7380062B2Mechanism in a multi-threaded microprocessor to maintain best case demand instruction redispatchIBM·Filed 2005·Granted May 27, 2008·5 cites·9 claims
- 2072US6557084B2Apparatus and method to improve performance of reads from and writes to shared memory locationsIBM·Filed 1999·Granted Apr 29, 2003·65 cites·27 claims
- 2171US10593420B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Mar 17, 2020·2 cites·11 claims
- 2270US10170199B2Testing content addressable memory and random access memoryIBM·Filed 2018·Granted Jan 1, 2019·2 cites·1 claims
- 2370US5790838APipelined memory interface and method for using the sameIBM·Filed 1996·Granted Aug 4, 1998·30 cites·19 claims
- 2470US5131085AHigh performance shared main storage interfaceIBM·Filed 1989·Granted Jul 14, 1992·44 cites·26 claims
- 2569US10175987B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2016·Granted Jan 8, 2019·1 cites·18 claims
- 2669US10079070B2Testing content addressable memory and random access memoryIBM·Filed 2016·Granted Sep 18, 2018·2 cites·9 claims
- 2767US5751990AAbridged virtual address cache directoryIBM·Filed 1994·Granted May 12, 1998·48 cites·18 claims
- 2865US8635408B2Controlling power of a cache based on predicting the instruction cache way for high power applicationsLEVENSTEIN SHELDON B·Filed 2011·Granted Jan 21, 2014·2 cites·18 claims
- 2965US5586331ADuplicated logic and interconnection system for arbitration among multiple information processorsIBM·Filed 1995·Granted Dec 17, 1996·39 cites·19 claims
- 3063US7962722B2Branch target address cache with hashed indicesIBM·Filed 2008·Granted Jun 14, 2011·2 cites·15 claims
- 3161US7603543B2Method, apparatus and program product for enhancing performance of an in-order processor with long stallsIBM·Filed 2005·Granted Oct 13, 2009·2 cites·3 claims
- 3260US10664279B2Instruction prefetching in a computer processor using a prefetch prediction vectorIBM·Filed 2019·Granted May 26, 2020·0 cites·18 claims
- 3359US7660965B2Method to optimize effective page number to real page number translation path from page table entries match resumption of execution streamIBM·Filed 2008·Granted Feb 9, 2010·1 cites·12 claims
- 3459US7197604B2Processor, data processing system and method for synchronzing access to data in shared memoryIBM·Filed 2004·Granted Mar 27, 2007·6 cites·18 claims
- 3556US11748104B2Microprocessor that fuses load and compare instructionsIBM·Filed 2020·Granted Sep 5, 2023·0 cites·6 claims
- 3654US7831775B2System and method for tracking changes in L1 data cache directoryIBM·Filed 2008·Granted Nov 9, 2010·0 cites·6 claims
- 3753US10983797B2Program instruction schedulingIBM·Filed 2019·Granted Apr 20, 2021·0 cites·17 claims
- 3852US7788450B2Method and apparatus for efficiently accessing both aligned and unaligned data from a memoryIBM·Filed 2007·Granted Aug 31, 2010·0 cites·12 claims
- 3952US7092270B2Apparatus and method for detecting multiple hits in CAM arraysIBM·Filed 2004·Granted Aug 15, 2006·8 cites·20 claims
- 4052US2024202127A1Sideband instruction address translationIBM·Filed 2022·Application pending·0 cites
- 4151US11593108B2Sharing instruction cache footprint between multiple threadsIBM·Filed 2021·Granted Feb 28, 2023·0 cites·25 claims
- 4250US11593109B2Sharing instruction cache lines between multiple threadsIBM·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 4350US5897662APseudo-random address generation mechanism that reduces address translation timeIBM·Filed 1995·Granted Apr 27, 1999·26 cites·1 claims
- 4450US5206941AFast store-through cache memoryIBM·Filed 1990·Granted Apr 27, 1993·23 cites·17 claims
- 4549US7401186B2System and method for tracking changes in L1 data cache directoryIBM·Filed 2005·Granted Jul 15, 2008·0 cites·3 claims
- 4648US7302525B2Method and apparatus for efficiently accessing both aligned and unaligned data from a memoryIBM·Filed 2005·Granted Nov 27, 2007·0 cites·3 claims
- 4748US5463741ADuplicated logic and interconnection system for arbitration among multiple information processorsIBM·Filed 1992·Granted Oct 31, 1995·15 cites·19 claims
- 4847US11163577B2Selectively supporting static branch prediction settings only in association with processor-designated types of instructionsIBM·Filed 2018·Granted Nov 2, 2021·0 cites·17 claims
- 4947US2006179258A1Method for detecting address match in a deeply pipelined processor designIBM·Filed 2005·Application pending·0 cites
- 5045US10528352B2Blocking instruction fetching in a computer processorIBM·Filed 2016·Granted Jan 7, 2020·0 cites·15 claims
Showing the top 50 of 56 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →