Method for detecting address match in a deeply pipelined processor design

Abstract

A method, apparatus and algorithm for quickly detecting an address match in a deeply pipelined processor design in a manner that may be implemented using a minimum of physical space in the critical area of the processor. The address comparison is split into two parts. The first part is a fast, partial address match comparator system. The second part is a slower, full address match comparator system. If a partial match between a requested address and a registry address is detected, then execution of the program or set of instructions requesting the address is temporarily suspended while a full address match check is performed. If the full address match check results in a full match between the requested address and a registry address, then the program or set of instructions is interrupted and stopped. Otherwise, the program or set of instructions continues execution.

1 . A method in a processor of performing an address match check, said method comprising: 
 requesting an address;    performing a partial match check comprising comparing a first set of bits contained in a requested address to a second set of bits contained in a registry address, wherein the registry address is stored in an address registry; and    performing a full match check if the first set of bits matches the second set of bits.    
   
   
       2 . The method of  claim 1  wherein the first set of hits comprises less than all of a plurality of bits contained in the requested address and the second set of bits comprises less than all of a plurality of bits contained in the registry address.  
   
   
       3 . The method of  claim 1  wherein the full match check comprises: 
 checking all of the bits of the requested address to all of the bits of the registry address.    
   
   
       4 . The method of  claim 1  wherein the full match check comprises: 
 comparing bits in the requested address not checked during the partial match check to bits in the registry address not checked during the partial match check to form a secondary match check; and    combining the partial match check and secondary match check such that all bits in the requested address are compared to all bits in the registry address.    
   
   
       5 . The method of  claim 1  wherein the steps of performing a partial match check and performing a full match check are performed if an enablement mechanism is activated.  
   
   
       6 . The method of  claim 1  wherein the step of performing the partial match check further comprises: 
 hashing the first set of bits and the second set of bits.    
   
   
       7 . The method of  claim 1  further comprising: 
 allowing a set of instructions requesting the requested address to continue execution if the first set of bits does not match the second set of bits.    
   
   
       8 . The method of  claim 1  further comprising: 
 transmitting a reject signal if the first set of bits matches the second set of bits, said reject signal operable to cause a set of instructions requesting the requested address to suspend execution.    
   
   
       9 . The method of  claim 8  further comprising: 
 the step of allowing the set of instructions to continue execution if the full match check does not result in a match between all of the bits of the registry address and all of the bits of the requested address.    
   
   
       10 . The method of  claim 8  further comprising: 
 transmitting an interrupt signal if the full match check results in a match between all of the bits in the registry address and all of the bits of the requested address, said interrupt signal operable to cause the set of instructions to stop execution.    
   
   
       11 . The method of  claim 1  wherein the bits of the registry address are transmitted 8 bits at a time to a means for performing the partial match check.  
   
   
       12 . The method of  claim 1  wherein the bits of the registry address are transmitted 8 bits at a time to a means for performing the full match check.  
   
   
       13 . A match check mechanism in a processor of a data processing system, the match check mechanism comprising: 
 an address registry operably connected to the processor, wherein the address registry contains a registry address, wherein the registry address comprises a plurality of bits, and wherein the registry address comprises one of a plurality of registry addresses;    a first comparator system operably connected to the processor, said first comparator system adapted to compare a requested address requested by a set of instructions to the registry address, wherein the requested address comprises a plurality of bits;    wherein the first comparator system is adapted to compare less than all of the bits of the registry address with less than all of the bits of the requested address, wherein the first comparator system produces an output comprising a partial match check, and wherein the partial match check results in a partial match if the bits of the registry address that are compared to the bits of the requested address match; and    a second comparator system operably connected to the processor, said second comparator system adapted to compare all of the bits of the registry address to all of the bits of the requested address if the partial match check results in a partial match, wherein the second comparator system produces an output comprising a full match check, and wherein the full match check results in a full match if all of the bits of the requested address match all of the bits of the registry address.    
   
   
       14 . The match check mechanism of  claim 13  further comprising an enablement mechanism, wherein: 
 the first comparator system and the second comparator system are operable if the enablement mechanism is activated; and    the first comparator system and the second comparator system are not operable if the enablement mechanism is not activated.    
   
   
       15 . The match check mechanism of  claim 13  wherein the first comparator system further comprises a first means for hashing a plurality of bits.  
   
   
       16 . The match check mechanism of  claim 15  wherein the first comparator system further comprises a second means for hashing a plurality of bits.  
   
   
       17 . The match check mechanism of  claim 16  wherein: 
 less than all of the bits of the requested address are provided to the first means for hashing; and    less than all of the bits of the registry address are provided to the second means for hashing.    
   
   
       18 . The match check mechanism of  claim 13  further comprising: 
 a means for transmitting a reject signal, said means adapted to transmit the reject signal if the partial match check results in a partial match, wherein the reject signal is operable to temporarily suspend execution of a set of instructions requesting the address.    
   
   
       19 . The match check mechanism of  claim 13  further comprising: 
 a means for transmitting an interrupt signal, said means adapted to transmit the interrupt signal if the full match check results in a full match, wherein the interrupt signal is operable to stop execution of a set of instructions requesting the address.    
   
   
       20 . A data processing system comprising: 
 a bus;    a memory operably connected to the bus, said memory having a plurality of associated addresses:    a processor operably connected to the bus;    a match check mechanism operably connected to the processor, the match check mechanism comprising: 
 an address registry operably connected to the processor, wherein the address registry contains a registry address, wherein the registry address comprises a plurality of bits, and wherein the registry address comprises one of a plurality of registry addresses;  
 a first comparator system operably connected to the processor, said first comparator system adapted to compare a requested address requested by a set of instructions to the registry address, wherein the requested address comprises a plurality of bits;  
 wherein the first comparator system is adapted to compare less than all of the bits of the registry address with less than all of the bits of the requested address;  
 wherein the first comparator system produces an output comprising a partial match check, and wherein the partial match check results in a partial match if the bits of the registry address that are compared to the bits of the requested address match;  
 a second comparator system operably connected to the processor, said second comparator system adapted to compare all of the bits of the registry address to all of the bits of the requested address if the partial match check results in a partial match;  
 wherein the second comparator system produces an output comprising a full match check, and wherein the full match check results in a full match if all of the bits of the requested address match all of the bits of the registry address.