Inventor · disambiguated record
David A. Schroter
Also filed as: SCHROTER DAVID A · SCHROTER DAVID ANDREW
26 granted patents·2 pending applications·520 citations·filing 1990–2017
96Inventor score
Technology areasG06F
Top patents by PatentIndex Score
28 records- 0192US7290261B2Method and logical apparatus for rename register reallocation in a simultaneous multi-threaded (SMT) processorIBM·Filed 2003·Granted Oct 30, 2007·98 cites·19 claims
- 0275US6401192B1Apparatus for software initiated prefetch and method thereforIBM·Filed 1998·Granted Jun 4, 2002·75 cites·8 claims
- 0368US7194603B2SMT flush arbitrationIBM·Filed 2003·Granted Mar 20, 2007·13 cites·9 claims
- 0467US10261791B2Bypassing memory access for a load instruction using instruction address mappingIBM·Filed 2017·Granted Apr 16, 2019·1 cites·20 claims
- 0566US10102002B2Dynamic issue masks for processor hang preventionIBM·Filed 2014·Granted Oct 16, 2018·1 cites·7 claims
- 0666US8549255B2Microprocessor, method and computer program product for direct page prefetch in millicode capable computer systemSCHROTER DAVID A·Filed 2008·Granted Oct 1, 2013·5 cites·17 claims
- 0765US9104399B2Dual issuing of complex instruction set instructionsBUSABA FADI·Filed 2009·Granted Aug 11, 2015·3 cites·19 claims
- 0865US7363625B2Method for changing a thread priority in a simultaneous multithread processorIBM·Filed 2003·Granted Apr 22, 2008·9 cites·2 claims
- 0964US6792524B1System and method cancelling a speculative branchIBM·Filed 1998·Granted Sep 14, 2004·48 cites·4 claims
- 1063US6338133B1Measured, allocation of speculative branch instructions to processor execution unitsIBM·Filed 1999·Granted Jan 8, 2002·42 cites·12 claims
- 1157US6275918B1Obtaining load target operand pre-fetch address from history table information upon incremented number of access indicator thresholdIBM·Filed 1999·Granted Aug 14, 2001·32 cites·17 claims
- 1256US8082467B2Triggering workaround capabilities based on events active in a processor pipelineALEXANDER GREGORY W·Filed 2009·Granted Dec 20, 2011·1 cites·21 claims
- 1354US6430680B1Processor and method of prefetching data based upon a detected strideIBM·Filed 1998·Granted Aug 6, 2002·29 cites·16 claims
- 1453US10108426B2Dynamic issue masks for processor hang preventionIBM·Filed 2015·Granted Oct 23, 2018·0 cites·7 claims
- 1552US2008109640A1Method For Changing A Thread Priority In A Simultaneous Multithread ProcessorIBM·Filed 2008·Application pending·0 cites
- 1651US7089406B2Method and apparatus for controlling program instruction completion timing for processor verificationIBM·Filed 2003·Granted Aug 8, 2006·5 cites·20 claims
- 1751US6035394ASystem for providing high performance speculative processing of complex load/store instructions by generating primitive instructions in the load/store unit and sequencer in parallelIBM·Filed 1998·Granted Mar 7, 2000·25 cites·20 claims
- 1850US7966474B2System, method and computer program product for translating storage elementsIBM·Filed 2008·Granted Jun 21, 2011·0 cites·16 claims
- 1950US6061785AData processing system having an apparatus for out-of-order register operations and method thereforIBM·Filed 1998·Granted May 9, 2000·24 cites·21 claims
- 2049US5269009AProcessor system with improved memory transfer meansIBM·Filed 1990·Granted Dec 7, 1993·25 cites·4 claims
- 2146US5764970AMethod and apparatus for supporting speculative branch and link/branch on count instructionsIBM·Filed 1995·Granted Jun 9, 1998·23 cites·22 claims
- 2244US2004215937A1Dynamically share interrupt handling logic among multiple threadsIBM·Filed 2003·Application pending·0 cites
- 2343US9880847B2Register file mappingIBM·Filed 2015·Granted Jan 30, 2018·0 cites·17 claims
- 2443US9075600B2Program status word dependency handling in an out of order microprocessor designALEXANDER GREGORY W·Filed 2010·Granted Jul 7, 2015·0 cites·18 claims
- 2543US5850542AMicroprocessor instruction hedge-fetching in a multiprediction branch environmentIBM·Filed 1995·Granted Dec 15, 1998·17 cites·11 claims
- 2643US5835714AMethod and apparatus for reservation of data buses between multiple storage control elementsIBM·Filed 1995·Granted Nov 10, 1998·14 cites·3 claims
- 2743US5416911APerformance enhancement for load multiple register instructionIBM·Filed 1993·Granted May 16, 1995·19 cites·10 claims
- 2842US5953510ABidirectional data bus reservation priority controls having token logicIBM·Filed 1991·Granted Sep 14, 1999·11 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →