Method For Changing A Thread Priority In A Simultaneous Multithread Processor

Abstract

An SMT system is designed to allow software alteration of thread priority. In one case, the system signals a change in a thread priority based on the state of instruction execution and in particular when the instruction has completed execution. To alter the priority of a thread, the software uses a special form of a “no operation” (NOP) instruction (hereafter termed thread priority NOP). When the thread priority NOP is dispatched, its special NOP is decoded in the decode unit of the IDU into an operation that writes a special code into the completion table for the thread priority NOP. A “trouble” bit is also set in the completion table that indicates which instruction group contains the thread priority NOP. The trouble bit indicates that special processing is required after instruction completion. The thread priority instruction is processed after completion using the special code to change a thread's priority.

1 - 6 . (canceled)  
   
   
       7 . A simultaneous multithread (SMT) processor comprising: 
 an instruction dispatch unit (IDU);    a thread priority selector in said IDU for selecting instructions from first and second threads for dispatch from said IDU;    a completion unit having a shared group completion table (GCT) for said first and second threads;    circuitry for generating a thread priority no operation (NOP) instruction to change an instruction execution priority of a thread selected from first and second threads;    circuitry for decoding said thread priority NOP instruction;    circuitry for writing a special code for modifying said instruction execution priority of said selected thread into said group completion table (GCT) in response to a dispatch of said thread priority NOP instruction;    circuitry for setting a trouble bit in said GCT corresponding to an instruction group containing said thread priority NOP instruction in response to said dispatch of said thread priority NOP instruction;    circuitry within said completion unit for determining that said instruction group has completed;    circuitry for processing said special code to generate priority data for setting a first priority value for said selected thread in response to said trouble bit being set to an ON logic state; and    circuitry for sending said first priority value to a thread priority selector controlling dispatching of instructions for said selected thread from said IDU and changing said selected thread's priority after said instruction group containing said thread priority NOP instruction has completed.    
   
   
       8 . The processor of  claim 7 , wherein said thread priority selector selects instructions from first and second thread instruction queues such that numbers of dispatched first and second thread instructions are in a proportion corresponding to each thread's instruction execution priority.  
   
   
       9 - 10 . (canceled)  
   
   
       11 . A data processing system comprising: 
 a central processing unit (CPU) having a simultaneous multithread (SMT processor;    a random access memory (RAM);    an input output (I/O) adapter;    a communications adapter;    a bus coupling said CPU, RAM, I/O adapter, and said communications adapter;    an instruction dispatch unit (IDU) in said SMT processor;    a thread priority selector in said IDU for selecting instructions from first and second threads for dispatch from said IDU;    a completion unit in said SMT having a shared group completion table (GCT) for first and second threads;    circuitry for generating a thread priority no operation (NOP) instruction to change an instruction execution priority of a thread selected from first and second threads;    circuitry for decoding said thread priority NOP instruction in said IDU;    circuitry for writing a special code for modifying said instruction execution priority of said selected thread into said group completion table (GCT) in response to a dispatch of said thread priority NOP instruction;    circuitry for setting a trouble bit in said GCT corresponding to an instruction group containing said thread priority NOP instruction in response to said dispatch of said thread priority NOP instruction;    circuitry within said completion unit for determining that said instruction group has completed;    circuitry for processing said special code to generate priority data for setting a first priority value for said selected thread in response to said trouble bit being set to an ON logic state; and    circuitry for sending said first priority value to a thread priority selector controlling dispatching of instructions for said selected thread in said IDU and changing said selected thread's priority after said instruction group containing said thread priority NOP instruction has completed.    
   
   
       12 . The data processing system of  claim 11 , wherein said thread priority selector selects instructions from first and second thread instruction queues such that numbers of dispatched first and second thread instructions are in a proportion corresponding to each thread's instruction execution priority.