Inventor · disambiguated record
David R. Stiles
Also filed as: STILES DAVID · STILES DAVID R
39 granted patents·2,579 citations·filing 1990–2006
98Inventor score
Top patents by PatentIndex Score
39 records- 0198US6499123B1Method and apparatus for debugging an integrated circuitADVANCED MICRO DEVICES INC·Filed 2000·Granted Dec 24, 2002·221 cites·5 claims
- 0298US5226126AProcessor having plurality of functional units for orderly retiring outstanding operations based upon its associated tagsNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 6, 1993·449 cites·8 claims
- 0396US5226130AMethod and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistencyNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 6, 1993·300 cites·4 claims
- 0493US5442757AComputer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsNEXGEN INC·Filed 1993·Granted Aug 15, 1995·147 cites·56 claims
- 0593US5163140ATwo-level branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1992·Granted Nov 10, 1992·145 cites·3 claims
- 0690US5781753ASemi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructionsADVANCED MICRO DEVICES INC·Filed 1995·Granted Jul 14, 1998·134 cites·61 claims
- 0790US5230068ACache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequenceNEXGEN MICROSYSTEMS·Filed 1990·Granted Jul 20, 1993·139 cites·5 claims
- 0889US5768575ASemi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructionsADVANCED MICRO DEVICES INC·Filed 1995·Granted Jun 16, 1998·166 cites·19 claims
- 0986US5515518ATwo-level branch prediction cacheNEXGEN INC·Filed 1994·Granted May 7, 1996·80 cites·31 claims
- 1084US6990121B1Method and apparatus for switching data of different protocolsREDBACK NETWORKS INC·Filed 2001·Granted Jan 24, 2006·47 cites·15 claims
- 1183US6975589B2Method and apparatus for a hybrid variable rate pipeREDBACK NETWORKS INC·Filed 2001·Granted Dec 13, 2005·21 cites·10 claims
- 1281US7050395B1Method and apparatus for disabling an interface between network element data processing unitsREDBACK NETWORKS INC·Filed 2001·Granted May 23, 2006·37 cites·16 claims
- 1381US5513330AApparatus for superscalar instruction predecoding using cached instruction lengthsNEXGEN INC·Filed 1993·Granted Apr 30, 1996·79 cites·3 claims
- 1479US6959008B2Alignment of TDM-based signals for packet transmission using framed and unframed operationsREDBACK NETWORKS INC·Filed 2001·Granted Oct 25, 2005·18 cites·46 claims
- 1578US7016300B2Protection mechanism for an optical ringREDBACK NETWORKS INC·Filed 2001·Granted Mar 21, 2006·14 cites·37 claims
- 1677US6765916B1Method and apparatus for processing of multiple protocols within data transmission signalsREDBACK NETWORKS INC·Filed 2000·Granted Jul 20, 2004·32 cites·48 claims
- 1776US6212629B1Method and apparatus for executing string instructionsADVANCED MICRO DEVICES INC·Filed 1998·Granted Apr 3, 2001·56 cites·22 claims
- 1875US5327547ATwo-level branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1992·Granted Jul 5, 1994·46 cites·12 claims
- 1973US6993047B1Any size and location of concatenated packet data across SONET frames in a SONET signalREDBACK NETWORKS INC·Filed 2000·Granted Jan 31, 2006·15 cites·27 claims
- 2073US5881265AComputer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsADVANCED MICRO DEVICES INC·Filed 1995·Granted Mar 9, 1999·47 cites·17 claims
- 2172US7460554B2Any size and location of concatenated packet data across SONET frames in a SONET signalREDBACK NETWORKS INC·Filed 2005·Granted Dec 2, 2008·4 cites·9 claims
- 2272US5093778AIntegrated single structure branch prediction cacheNEXGEN MICROSYSTEMS·Filed 1990·Granted Mar 3, 1992·61 cites·6 claims
- 2368US5826052AMethod and apparatus for concurrent access to multiple physical cachesADVANCED MICRO DEVICES INC·Filed 1995·Granted Oct 20, 1998·62 cites·15 claims
- 2467US5511175AMethod an apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistencyNEXGEN INC·Filed 1994·Granted Apr 23, 1996·40 cites·11 claims
- 2566US7277447B2Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous payload envelopes in synchronous optical networksREDBACK NETWORKS INC·Filed 2001·Granted Oct 2, 2007·7 cites·17 claims
- 2663US6425075B1Branch prediction device with two levels of branch prediction cacheADVANCED MICRO DEVICES INC·Filed 1999·Granted Jul 23, 2002·26 cites·14 claims
- 2762US6067616ABranch prediction device with two levels of branch prediction cacheADVANCED MICRO DEVICES INC·Filed 1996·Granted May 23, 2000·27 cites·11 claims
- 2858US7209436B1Method and apparatus for variable rate pipesREDBACK NETWORKS INC·Filed 2001·Granted Apr 24, 2007·3 cites·62 claims
- 2958US6021471AMultiple level cache control system with address and data pipelinesADVANCED MICRO DEVICES INC·Filed 1994·Granted Feb 1, 2000·35 cites·5 claims
- 3055US7158540B1Ring network element and the ring network architectures it enablesREDBACK NETWORKS INC·Filed 2001·Granted Jan 2, 2007·11 cites·53 claims
- 3154US5682492AComputer processor with distributed pipeline control that allows functional units to complete operations out of order while maintaining precise interruptsADVANCED MICRO DEVICES INC·Filed 1995·Granted Oct 28, 1997·21 cites·54 claims
- 3252US8228958B1Ring network element and the ring network architectures it enablesSTILES DAVID R·Filed 2006·Granted Jul 24, 2012·1 cites·16 claims
- 3352US5905997ASet-associative cache memory utilizing a single bank of physical memoryAMD INC·Filed 1996·Granted May 18, 1999·26 cites·14 claims
- 3451US5649137AMethod and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistencyADVANCED MICRO DEVICES INC·Filed 1996·Granted Jul 15, 1997·25 cites·2 claims
- 3548US7272157B2Any size and location of concatenated packet data across SONET frames in a SONET signalREDBACK NETWORKS INC·Filed 2005·Granted Sep 18, 2007·0 cites·6 claims
- 3647US5764556AMethod and apparatus for performing floating point additionADVANCED MICRO DEVICES INC·Filed 1996·Granted Jun 9, 1998·23 cites·2 claims
- 3741US7324539B1Method and apparatus for processing channelized and unchannelized data within a signalREDBACK NETWORKS INC·Filed 2002·Granted Jan 29, 2008·0 cites·41 claims
- 3838US5748932ACache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequenceADVANCED MICRO DEVICES INC·Filed 1995·Granted May 5, 1998·9 cites·10 claims
- 3933US5832259AApparatus for superscalar instruction pre-decoding using cached instruction lengthsADVANCED MICRO DEVICES INC·Filed 1996·Granted Nov 3, 1998·5 cites·12 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →