Inventor · disambiguated record
David J. Widiger
Also filed as: WIDIGER DAVID J · WIDIGER DAVID JAMES
27 granted patents·3 pending applications·297 citations·filing 1996–2024
96Inventor score
Top patents by PatentIndex Score
30 records- 0189US11176308B1Extracting parasitic capacitance from circuit designsIBM·Filed 2020·Granted Nov 16, 2021·3 cites·20 claims
- 0287US6601222B1Coupled noise estimation and avoidance of noise-failure using global routing informationIBM·Filed 2000·Granted Jul 29, 2003·53 cites·24 claims
- 0386US7346867B2Method for estimating propagation noise based on effective capacitance in an integrated circuit chipIBM·Filed 2005·Granted Mar 18, 2008·18 cites·13 claims
- 0484US9886541B2Process for improving capacitance extraction performanceIBM·Filed 2015·Granted Feb 6, 2018·4 cites·20 claims
- 0584US6523149B1Method and system to improve noise analysis performance of electrical circuitsIBM·Filed 2000·Granted Feb 18, 2003·42 cites·45 claims
- 0681US10360338B2Method for improving capacitance extraction performance by approximating the effect of distant shapesIBM·Filed 2016·Granted Jul 23, 2019·5 cites·9 claims
- 0778US7685549B2Method of constrained aggressor set selection for crosstalk induced noiseIBM·Filed 2007·Granted Mar 23, 2010·10 cites·24 claims
- 0877US6510540B1Windowing mechanism for reducing pessimism in cross-talk analysis of digital chipsIBM·Filed 2000·Granted Jan 21, 2003·29 cites·28 claims
- 0976US11314916B2Capacitance extractionIBM·Filed 2020·Granted Apr 26, 2022·1 cites·20 claims
- 1072US6131182AMethod and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macrosIBM·Filed 1997·Granted Oct 10, 2000·72 cites·31 claims
- 1169US10685168B2Capacitance extraction for floating metal in integrated circuitIBM·Filed 2018·Granted Jun 16, 2020·1 cites·20 claims
- 1269US7844435B2Integrated circuit chip having on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniquesIBM·Filed 2007·Granted Nov 30, 2010·4 cites·5 claims
- 1368US8645899B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2009·Granted Feb 4, 2014·4 cites·8 claims
- 1468US8612918B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Dec 17, 2013·2 cites·17 claims
- 1567US8239804B2Method for calculating capacitance gradients in VLSI layouts using a shape processing engineELFADEL IBRAHIM M·Filed 2009·Granted Aug 7, 2012·4 cites·19 claims
- 1662US7475372B2Methods for computing Miller-factor using coupled peak noiseIBM·Filed 2005·Granted Jan 6, 2009·2 cites·11 claims
- 1759US7319946B2Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniquesIBM·Filed 2002·Granted Jan 15, 2008·6 cites·5 claims
- 1855US8495540B2Generating capacitance look-up tables for wiring patterns in the presence of metal fillsELFADEL IBRAHIM M·Filed 2012·Granted Jul 23, 2013·0 cites·21 claims
- 1954US9317644B2Generating capacitance look-up tables for wiring patterns in the presence of metal fillsGLOBALFOUNDRIES INC·Filed 2013·Granted Apr 19, 2016·0 cites·20 claims
- 2054US8245169B2Generating capacitance look-up tables for wiring patterns in the presence of metal fillsELFADEL IBRAHIM M·Filed 2009·Granted Aug 14, 2012·0 cites·15 claims
- 2154US2025245411A1Wiring pattern-based parasitic capacitance extractionIBM·Filed 2024·Application pending·0 cites
- 2254US2025156622A1Process of fitting function parameters that facilitates accurate pattern-based 3d capacitance extractionIBM·Filed 2023·Application pending·0 cites
- 2353US10354041B2Process for improving capacitance extraction performanceIBM·Filed 2017·Granted Jul 16, 2019·0 cites·1 claims
- 2453US6086238AMethod and system for shape processing within an integrated circuit layout for parasitic capacitance estimationIBM·Filed 1996·Granted Jul 11, 2000·27 cites·9 claims
- 2550US10929581B2Selectively grounding fill wiresIBM·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 2648US8539428B2Method for extracting information for a circuit designWIDIGER DAVID J·Filed 2012·Granted Sep 17, 2013·0 cites·15 claims
- 2748US8136069B2Accurate approximation of resistance in a wire with irregular biasing and determination of interconnect capacitances in VLSI layouts in the presence of Catastrophic Optical Proximity CorrectionDEWEY III LEWIS WILLIAM·Filed 2009·Granted Mar 13, 2012·0 cites·15 claims
- 2848US6005416ACompiled self-resetting CMOS logic array macrosIBM·Filed 1997·Granted Dec 21, 1999·10 cites·38 claims
- 2945US10169516B2Methods and computer program products for via capacitance extractionIBM·Filed 2015·Granted Jan 1, 2019·0 cites·20 claims
- 3037US2017177776A1Partitioning of wiring for capacitance extraction without loss in accuracyIBM·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →