Inventor · disambiguated record
Derick G. Behrends
Also filed as: BEHRENDS DERICK G · BEHRENDS DERICK GARDNER
54 granted patents·16 pending applications·227 citations·filing 2002–2016
98Inventor score
Top patents by PatentIndex Score
70 records- 0192US8520429B2Data dependent SRAM write assistBEHRENDS DERICK G·Filed 2011·Granted Aug 27, 2013·18 cites·2 claims
- 0290US9058861B2Power management SRAM write bit line drive circuitIBM·Filed 2012·Granted Jun 16, 2015·13 cites·20 claims
- 0390US8578304B1Implementing mulitple mask lithography timing variation mitigationBEHRENDS DERICK G·Filed 2012·Granted Nov 5, 2013·7 cites·17 claims
- 0489US8159260B1Delay chain burn-in for increased repeatability of physically unclonable functionsBEHRENDS DERICK GARDNER·Filed 2010·Granted Apr 17, 2012·15 cites·13 claims
- 0588US8842487B2Power management domino SRAM bit line discharge circuitIBM·Filed 2013·Granted Sep 23, 2014·9 cites·1 claims
- 0684US7535776B1Circuit for improved SRAM write around with reduced read access penaltyIBM·Filed 2008·Granted May 19, 2009·16 cites·1 claims
- 0784US7502276B1Method and apparatus for multi-word write in domino read SRAMsIBM·Filed 2008·Granted Mar 10, 2009·15 cites·1 claims
- 0883US7525367B2Method for implementing level shifter circuits for integrated circuitsIBM·Filed 2006·Granted Apr 28, 2009·12 cites·3 claims
- 0982US7924633B2Implementing boosted wordline voltage in memoriesIBM·Filed 2009·Granted Apr 12, 2011·13 cites·17 claims
- 1082US7505340B1Method for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Mar 17, 2009·10 cites·6 claims
- 1179US7737757B2Low power level shifting latch circuits with gated feedback for high speed integrated circuitsIBM·Filed 2008·Granted Jun 15, 2010·9 cites·15 claims
- 1276US8669800B2Implementing power saving self powering down latch structureBEHRENDS DERICK G·Filed 2012·Granted Mar 11, 2014·4 cites·20 claims
- 1372US9082484B1Partial update in a ternary content addressable memoryIBM·Filed 2013·Granted Jul 14, 2015·2 cites·12 claims
- 1471US8711606B2Data security for dynamic random access memory using body bias to clear data at power-upIBM·Filed 2013·Granted Apr 29, 2014·3 cites·9 claims
- 1570US9583938B2Electrostatic discharge protection device with power managementIBM·Filed 2015·Granted Feb 28, 2017·1 cites·19 claims
- 1667US7626851B2Method to improve performance of SRAM cells, SRAM cell, SRAM array, and write circuitIBM·Filed 2007·Granted Dec 1, 2009·6 cites·2 claims
- 1766US9287873B2Level shifter for a time-varying inputIBM·Filed 2014·Granted Mar 15, 2016·1 cites·6 claims
- 1866US7035127B1Method and sum addressed cell encoder for enhanced compare and search timing for CAM compareIBM·Filed 2004·Granted Apr 25, 2006·14 cites·16 claims
- 1965US8344782B2Method and apparatus to limit circuit delay dependence on voltage for single phase transitionIBM·Filed 2009·Granted Jan 1, 2013·4 cites·17 claims
- 2063US9153638B2Integrated decoupling capacitor utilizing through-silicon viaIBM·Filed 2013·Granted Oct 6, 2015·1 cites·8 claims
- 2163US7443744B2Method for reducing wiring and required number of redundant elementsIBM·Filed 2006·Granted Oct 28, 2008·4 cites·4 claims
- 2263US7133320B2Flood mode implementation for continuous bitline local evaluation circuitIBM·Filed 2004·Granted Nov 7, 2006·11 cites·19 claims
- 2362US8427894B2Implementing single bit redundancy for dynamic SRAM circuit with any bit decodeBEHRENDS DERICK G·Filed 2010·Granted Apr 23, 2013·3 cites·20 claims
- 2461US8467230B2Data security for dynamic random access memory using body bias to clear data at power-upBEHRENDS DERICK GARDNER·Filed 2010·Granted Jun 18, 2013·2 cites·6 claims
- 2561US7788554B2Design structure embodied in a machine readable medium for implementing SRAM cell write performance evaluationIBM·Filed 2007·Granted Aug 31, 2010·3 cites·16 claims
- 2660US8675427B2Implementing RC and coupling delay correction for SRAMBEHRENDS DERICK G·Filed 2012·Granted Mar 18, 2014·2 cites·20 claims
- 2760US7724585B2Implementing local evaluation of domino read SRAM with enhanced SRAM cell stabilityIBM·Filed 2008·Granted May 25, 2010·4 cites·18 claims
- 2859US9424389B2Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeperIBM·Filed 2014·Granted Aug 23, 2016·0 cites·15 claims
- 2959US8395963B2Data security for dynamic random access memory at power-upBEHRENDS DERICK G·Filed 2010·Granted Mar 12, 2013·2 cites·11 claims
- 3057US9218880B2Partial update in a ternary content addressable memoryIBM·Filed 2014·Granted Dec 22, 2015·0 cites·5 claims
- 3157US7911827B2Implementing enhanced SRAM stability and enhanced chip yield with configurable wordline voltage levelsIBM·Filed 2009·Granted Mar 22, 2011·3 cites·18 claims
- 3257US7751266B2High performance read bypass test for SRAM circuitsIBM·Filed 2008·Granted Jul 6, 2010·3 cites·18 claims
- 3357US7224594B2Glitch protect valid cell and method for maintaining a desired state valueIBM·Filed 2005·Granted May 29, 2007·4 cites·20 claims
- 3456US7675794B2Design structure for improving performance of SRAM cells, SRAM cell, SRAM array, and write circuitIBM·Filed 2007·Granted Mar 9, 2010·3 cites·3 claims
- 3555US9142560B2Layout to minimize FET variation in small dimension photolithographyIBM·Filed 2014·Granted Sep 22, 2015·0 cites·3 claims
- 3655US7714630B2Method and apparatus to limit circuit delay dependence on voltageIBM·Filed 2008·Granted May 11, 2010·2 cites·1 claims
- 3754US8824196B2Single cycle data copy for two-port SRAMBEHRENDS DERICK G·Filed 2012·Granted Sep 2, 2014·1 cites·21 claims
- 3854US7681095B2Methods and apparatus for testing integrated circuitsIBM·Filed 2008·Granted Mar 16, 2010·2 cites·9 claims
- 3953US9396303B2Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeperIBM·Filed 2015·Granted Jul 19, 2016·0 cites·5 claims
- 4053US7400550B2Delay mechanism for unbalanced read/write paths in domino SRAM arraysIBM·Filed 2006·Granted Jul 15, 2008·2 cites·3 claims
- 4151US7971164B2Assessing resources required to complete a VLSI designIBM·Filed 2008·Granted Jun 28, 2011·0 cites·20 claims
- 4250US9496712B1Electrostatic discharge protection device with power managementIBM·Filed 2016·Granted Nov 15, 2016·0 cites·1 claims
- 4350US9312858B2Level shifter for a time-varying inputIBM·Filed 2014·Granted Apr 12, 2016·0 cites·18 claims
- 4450US9196671B2Integrated decoupling capacitor utilizing through-silicon viaIBM·Filed 2012·Granted Nov 24, 2015·0 cites·8 claims
- 4549US7768851B2Apparatus for implementing SRAM cell write performance evaluationIBM·Filed 2009·Granted Aug 3, 2010·1 cites·13 claims
- 4648US2010030804A1Synchronization of Locations in Real and Virtual WorldsIBM·Filed 2008·Application pending·0 cites
- 4747US8860141B2Layout to minimize FET variation in small dimension photolithographyBEHRENDS DERICK GARDNER·Filed 2012·Granted Oct 14, 2014·0 cites·3 claims
- 4847US8108739B2High-speed testing of integrated devicesADAMS CHAD A·Filed 2008·Granted Jan 31, 2012·1 cites·21 claims
- 4943US2014092672A1Power management domino sram bit line discharge circuitIBM·Filed 2012·Application pending·0 cites
- 5043US2014126273A1Power management sram global bit line precharge circuitIBM·Filed 2012·Application pending·0 cites
Showing the top 50 of 70 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →