Power management domino sram bit line discharge circuit

Abstract

A domino static random access memory (SRAM) having one or more SRAM memory cells connected with a local bit line is disclosed. The SRAM may include a global bit line, a first precharge device connected between a voltage supply and the local bit line, and a second precharge device connected between the voltage supply and the global bit line. In addition the SRAM may include a global bit line discharge logic connected with the global bit line and the local bit line. The global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.

1 . A domino static random access memory (SRAM) comprising:
 one or more SRAM memory cells connected with a local bit line;   a global bit line;   a first precharge device connected between a voltage supply and the local bit line;   a second precharge device connected between the voltage supply and the global bit line; and   a global bit line discharge logic connected with the global bit line and the local bit line, wherein the global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.   
     
     
         2 . The SRAM of  claim 1 , wherein the global bit line discharge logic is a PFET transistor having a drain connected to a ground, a source connected to the global bit line, and a gate connected to the local bit line. 
     
     
         3 . The SRAM of  claim 1 , wherein the local bit line is a complement local bit line. 
     
     
         4 - 5 . (canceled) 
     
     
         6 . A design structure tangibly embodied in a machine-readable storage medium used in a design process of an SRAM, the design structure having elements that, when processed in a semiconductor manufacturing facility, produce an SRAM that comprises:
 one or more SRAM memory cells connected with a local bit line;   a global bit line;   a first precharge device connected between a voltage supply and the local bit line;   a second precharge device connected between the voltage supply and the global bit line; and   a global bit line discharge logic connected with the global bit line and the local bit line, wherein the global bit line discharge logic is adapted to draw the global bit line to a voltage below a precharge voltage and above a ground voltage during a read operation.   
     
     
         7 . The design structure of  claim 6 , wherein the design structure comprises a Netlist which describes the SRAM. 
     
     
         8 . The design structure of  claim 6 , wherein the design structure resides on a storage medium as a data format used for the exchange of layout data of integrated circuits. 
     
     
         9 . The design structure of  claim 6 , wherein the design structure includes at least one set of test data files, characterization data, verification data, or design specifications. 
     
     
         10 . The design structure of  claim 6 , wherein the global bit line discharge logic is a PFET transistor having a drain connected to a ground, a source connected to the global bit line, and a gate connected to the local bit line. 
     
     
         11 . The design structure of  claim 6 , wherein the local bit line is a complement local bit line.