Inventor · disambiguated record
Devika Sarkar Grant
Also filed as: GRANT DEVIKA S · GRANT DEVIKA SARKAR
8 granted patents·5 pending applications·2 citations·filing 2021–2025
73Inventor score
Top patents by PatentIndex Score
13 records- 0185US12394660B2Buried power rail after replacement metal gateIBM·Filed 2021·Granted Aug 19, 2025·1 cites·17 claims
- 0284US12243913B2Self-aligned backside contact integration for transistorsIBM·Filed 2022·Granted Mar 4, 2025·1 cites·17 claims
- 0362US2025132163A1Engineering epi stacks for extreme wafer thinningAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 0460US12494408B2Double patterned microcooler having alternating fin widthsIBM·Filed 2021·Granted Dec 9, 2025·0 cites·16 claims
- 0560US12438085B2Via to backside power rail through active regionIBM·Filed 2022·Granted Oct 7, 2025·0 cites·25 claims
- 0658US12417926B2Circuit interconnect structureIBM·Filed 2021·Granted Sep 16, 2025·0 cites·20 claims
- 0757US12148699B2High aspect ratio buried power rail metallizationIBM·Filed 2022·Granted Nov 19, 2024·0 cites·15 claims
- 0856US2025391708A1Substrate processing for improved wafer thickness uniformityAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
- 0955US12046511B2Selective metal residue and liner cleanse for post-subtractive etchIBM·Filed 2021·Granted Jul 23, 2024·0 cites·11 claims
- 1051US2024105554A1Transistors with via-to-backside power rail spacersIBM·Filed 2022·Application pending·0 cites
- 1151US2025316491A1Integrated substrate thinningAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
- 1250US2023369218A1Interlevel via for stacked field-effect transistor deviceIBM·Filed 2022·Application pending·0 cites
- 1349US12334398B2Multilayer dielectric stack for damascene top-via integrationIBM·Filed 2021·Granted Jun 17, 2025·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →