Inventor · disambiguated record
Deborah T. Marr
Also filed as: MARR DEBORAH · MARR DEBORAH T
46 granted patents·13 pending applications·519 citations·filing 1999–2025
98Inventor score
Top patents by PatentIndex Score
59 records- 0197US11093277B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2020·Granted Aug 17, 2021·6 cites·25 claims
- 0297US10146738B2Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix dataINTEL CORP·Filed 2016·Granted Dec 4, 2018·43 cites·20 claims
- 0396US11693691B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2021·Granted Jul 4, 2023·4 cites·11 claims
- 0495US7363474B2Method and apparatus for suspending execution of a thread until a specified memory access occursINTEL CORP·Filed 2001·Granted Apr 22, 2008·104 cites·18 claims
- 0594US10180928B2Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributionsINTEL CORP·Filed 2016·Granted Jan 15, 2019·15 cites·20 claims
- 0694US6671795B1Method and apparatus for pausing execution in a processor or the likeINTEL CORP·Filed 2000·Granted Dec 30, 2003·80 cites·33 claims
- 0793US11373088B2Machine learning accelerator mechanismINTEL CORP·Filed 2017·Granted Jun 28, 2022·28 cites·25 claims
- 0893US11113053B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2019·Granted Sep 7, 2021·8 cites·20 claims
- 0993US10776110B2Apparatus and method for adaptable and efficient lane-wise tensor processingINTEL CORP·Filed 2018·Granted Sep 15, 2020·20 cites·27 claims
- 1093US10489063B2Memory-to-memory instructions to accelerate sparse-matrix by dense-vector and sparse-vector by dense-vector multiplicationINTEL CORP·Filed 2016·Granted Nov 26, 2019·10 cites·20 claims
- 1193US7127561B2Coherency techniques for suspending execution of a thread until a specified memory access occursINTEL CORP·Filed 2001·Granted Oct 24, 2006·95 cites·36 claims
- 1291US11416281B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2016·Granted Aug 16, 2022·4 cites·28 claims
- 1390US12135981B2Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2023·Granted Nov 5, 2024·1 cites·20 claims
- 1490US12014265B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2023·Granted Jun 18, 2024·1 cites·20 claims
- 1589US10275247B2Apparatuses and methods to accelerate vector multiplication of vector elements having matching indicesINTEL CORP·Filed 2015·Granted Apr 30, 2019·7 cites·24 claims
- 1688US9996361B2Byte and nibble sort instructions that produce sorted destination register and destination index mappingINTEL CORP·Filed 2015·Granted Jun 12, 2018·5 cites·20 claims
- 1787US11636327B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2017·Granted Apr 25, 2023·6 cites·20 claims
- 1886US11328037B2Memory-size- and bandwidth-efficient method for feeding systolic array matrix multipliersINTEL CORP·Filed 2017·Granted May 10, 2022·5 cites·21 claims
- 1986US10452551B2Programmable memory prefetcher for prefetching multiple cache lines based on data in a prefetch engine control registerINTEL CORP·Filed 2016·Granted Oct 22, 2019·5 cites·18 claims
- 2086US10387037B2Microarchitecture enabling enhanced parallelism for sparse linear algebra operations having write-to-read dependenciesINTEL CORP·Filed 2016·Granted Aug 20, 2019·5 cites·20 claims
- 2185US12039435B2Machine learning accelerator mechanismINTEL CORP·Filed 2022·Granted Jul 16, 2024·1 cites·24 claims
- 2285US11216722B2Hardware accelerator template and design framework for implementing recurrent neural networksINTEL CORP·Filed 2016·Granted Jan 4, 2022·5 cites·19 claims
- 2385US10049080B2Asymmetric performance multicore architecture with same instruction set architectureINTEL CORP·Filed 2017·Granted Aug 14, 2018·3 cites·24 claims
- 2484US2025384257A1Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2025·Application pending·0 cites
- 2582US2025123881A1Systems, methods, and apparatuses for heterogeneous computingINTEL CORP·Filed 2024·Application pending·0 cites
- 2681US12380326B2Machine learning sparse computation mechanism for arbitrary neural networks, arithmetic compute microarchitecture, and sparsity for training mechanismINTEL CORP·Filed 2024·Granted Aug 5, 2025·0 cites·20 claims
- 2781US10915328B2Apparatus and method for a high throughput parallel co-processor and interconnect with low offload latencyINTEL CORP·Filed 2018·Granted Feb 9, 2021·3 cites·30 claims
- 2878US12417380B2Machine learning accelerator mechanismINTEL CORP·Filed 2024·Granted Sep 16, 2025·0 cites·20 claims
- 2974US10409613B2Processing devices to perform a key value lookup instructionINTEL CORP·Filed 2015·Granted Sep 10, 2019·2 cites·19 claims
- 3071US2023359695A1Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix MultipliersINTEL CORP·Filed 2023·Application pending·0 cites
- 3169US10372507B2Compute engine architecture to support data-parallel loops with reduction operationsINTEL CORP·Filed 2016·Granted Aug 6, 2019·2 cites·19 claims
- 3269US8516024B2Establishing thread priority in a processor or the likeMARR DEBORAH T·Filed 2011·Granted Aug 20, 2013·3 cites·16 claims
- 3368US9081688B2Obtaining data for redundant multithreading (RMT) executionHINTON GLENN J·Filed 2008·Granted Jul 14, 2015·4 cites·15 claims
- 3468US8041754B1Establishing thread priority in a processor or the likeINTEL CORP·Filed 2000·Granted Oct 18, 2011·11 cites·9 claims
- 3567US2022121917A1Hardware accelerator template and design framework for implementing recurrent neural networksINTEL CORP·Filed 2021·Application pending·0 cites
- 3666US2023064381A1Memory-Size- and Bandwidth-Efficient Method for Feeding Systolic Array Matrix MultipliersINTEL CORP·Filed 2022·Application pending·0 cites
- 3765US7143242B2Dynamic priority external transaction systemINTEL CORP·Filed 2003·Granted Nov 28, 2006·8 cites·31 claims
- 3863US10198264B2Sorting data and merging sorted data in an instruction set architectureINTEL CORP·Filed 2015·Granted Feb 5, 2019·1 cites·25 claims
- 3962US10740281B2Asymmetric performance multicore architecture with same instruction set architectureINTEL CORP·Filed 2018·Granted Aug 11, 2020·0 cites·21 claims
- 4061US8793689B2Redundant multithreading processorHINTON GLENN J·Filed 2010·Granted Jul 29, 2014·1 cites·23 claims
- 4160US9594648B2Controlling non-redundant execution in a redundant multithreading (RMT) processorHINTON GLENN J·Filed 2008·Granted Mar 14, 2017·2 cites·12 claims
- 4259US10635448B2Byte and nibble sort instructions that produce sorted destination register and destination index mappingINTEL CORP·Filed 2018·Granted Apr 28, 2020·0 cites·20 claims
- 4359US9569278B2Asymmetric performance multicore architecture with same instruction set architectureGEORGE VARGHESE·Filed 2011·Granted Feb 14, 2017·1 cites·20 claims
- 4456US7451296B2Method and apparatus for pausing execution in a processor or the likeINTEL CORP·Filed 2003·Granted Nov 11, 2008·3 cites·17 claims
- 4552US10423411B2Data element comparison processors, methods, systems, and instructionsINTEL CORP·Filed 2015·Granted Sep 24, 2019·0 cites·23 claims
- 4651US10831505B2Architecture and method for data parallel single program multiple data (SPMD) executionINTEL CORP·Filed 2018·Granted Nov 10, 2020·0 cites·29 claims
- 4751US2008034190A1Method and apparatus for suspending execution of a thread until a specified memory access occursRODGERS DION·Filed 2007·Application pending·0 cites
- 4850US10437562B2Apparatus and method for processing sparse dataINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·23 claims
- 4948US10289752B2Accelerator for gather-update-scatter operations including a content-addressable memory (CAM) and CAM controllerINTEL CORP·Filed 2016·Granted May 14, 2019·0 cites·20 claims
- 5047US11416248B2Method and system for efficient floating-point compressionINTEL CORP·Filed 2020·Granted Aug 16, 2022·0 cites·21 claims
Showing the top 50 of 59 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Deborah T. Marr files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →