Method and apparatus for suspending execution of a thread until a specified memory access occurs

Abstract

Techniques for suspending execution of a thread until a specified memory access occurs. In one embodiment, a processor includes multiple execution units capable of executing multiple threads. A first thread includes an instruction that specifies a monitor address. Suspend logic suspends execution of the first thread, and a monitor causes resumption of the first thread in response to an access to the specified monitor address.

1 - 69 . (canceled)  
   
   
       70 . A processor comprising: 
 a plurality of execution units to execute a plurality of threads;    suspend logic to suspend execution of a first thread of the plurality of threads upon execution of a first instruction within the first thread while at least one of the plurality of threads remains active; and    a memory access monitor to signal resumption of the first thread in response to a memory access to a specified memory location.    
   
   
       71 . The processor of  claim 70  wherein the memory access monitor is to cause resumption of the first thread in response to events that cause a translation look-aside buffer to be flushed.  
   
   
       72 . The processor of  claim 70  wherein the memory access monitor is to cause resumption of the first thread in response to a write to a predetermined control register.  
   
   
       73 . The processor of  claim 72  further comprising resume logic receive signals to cause resumption in the execution of the first thread.  
   
   
       74 . The processor of  claim 70  wherein the suspend logic further sets a monitor address as the specified memory location in response to execution of a second instruction in the first thread so that resumption of the first thread occurs only in response to the memory access to the monitor address.  
   
   
       75 . The processor of  claim 70  wherein the suspend logic is only to suspend the first thread in response to a write access to the specified memory location.  
   
   
       76 . The processor of  claim 70  wherein the suspend logic is only to suspend the first thread if the memory access is a write access to a selected memory.  
   
   
       77 . The processor of  claim 76  wherein the selected memory type is a write-back type of memory.  
   
   
       78 . The processor of  claim 70  further comprising an instruction buffer adapted as either a single partition dedicated to one thread or multiple partitions to be used by the plurality of threads.  
   
   
       79 . The processor of  claim 74  wherein the processor is capable of out-of-order execution and wherein the second instruction is followed by a store fence that ensures all store operations are processed at the time the first instruction completes execution.  
   
   
       80 . The processor of  claim 74  wherein the second instruction is an instruction having only implicit operands.  
   
   
       81 . The processor of  claim 70  further comprising: 
 coherency logic to perform a read line transaction in conjunction with suspending the first thread.    
   
   
       82 . The processor of  claim 81  wherein the coherency logic is to perform a cache line flush to flush internal caches in conjunction with suspending the first thread.  
   
   
       83 . A processor comprising: 
 a front end to receive a first instruction and a second instruction, the first instruction having an implicit operand from a predetermined register indicating a monitor address;    execution resources to execute the first instruction and the second instruction and to enter a first implementation dependent state in response to the second instruction if the first instruction has been executed and no break events have occurred after execution of the first instruction; and    a monitor to cause an exit from the first implementation dependent state in response to a memory access to the monitor address.    
   
   
       84 . The processor of  claim 83  wherein the implicit operand is to indicate a linear address, and wherein the processor further comprises address translation logic to translate the linear address to obtain the monitor address which is a physical address.  
   
   
       85 . The processor of  claim 83  further comprising: 
 coherency logic to ensure that no cache in another processor coupled to the processor stores information at the monitor address in a modified or exclusive state.    
   
   
       86 . The processor of  claim 83  wherein the coherency logic is to assert a hit signal in response to another processor snooping the monitor address.  
   
   
       87 . The processor of  claim 85  wherein the coherency logic is to assert a hit signal in response to another processor snooping the monitor address.  
   
   
       88 . A method comprising: 
 executing a plurality of threads;    suspending execution of a first thread of the plurality of threads upon execution of a first instruction within the first thread while at least one of the plurality of threads remains active;    passively monitoring for an event; and    resuming execution of the first thread in response to detecting the event.    
   
   
       89 . The method of  claim 88 , wherein the passively monitoring of the event includes monitoring for a memory access to a specified memory location.  
   
   
       90 . The method of  claim 88  wherein the passively monitoring of the event includes monitoring for an event without undergoing a spin-wait loop.  
   
   
       91 . The method of  claim 89  wherein prior to suspending the first thread, the method further comprises setting a monitor address as the specified memory location in response to execution of a second instruction in the first thread so that resumption of the first thread occurs in response to the memory access to the monitor address.