Inventor · disambiguated record
Debjit Sinha
Also filed as: SINHA DEBJIT
36 granted patents·3 pending applications·131 citations·filing 2007–2022
96Inventor score
Top patents by PatentIndex Score
39 records- 0191US9342639B1Method of hierarchical timing closure of VLSI circuits using partially disruptive feedback assertionsIBM·Filed 2015·Granted May 17, 2016·12 cites·16 claims
- 0290US10970455B1Apportionment aware hierarchical timing optimizationIBM·Filed 2020·Granted Apr 6, 2021·3 cites·18 claims
- 0388US10346569B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Jul 9, 2019·4 cites·1 claims
- 0487US8683409B2Performing statistical timing analysis with non-separable statistical and deterministic variationsIBM·Filed 2013·Granted Mar 25, 2014·8 cites·25 claims
- 0585US9690899B2Prioritized path tracing in statistical timing analysis of integrated circuitsIBM·Filed 2015·Granted Jun 27, 2017·5 cites·17 claims
- 0684US9400864B2System and method for maintaining slack continuity in incremental statistical timing analysisIBM·Filed 2014·Granted Jul 26, 2016·7 cites·13 claims
- 0784US8122404B2Performing a statistical timing abstraction for a hierarchical timing analysis of VLSI circuitsSINHA DEBJIT·Filed 2009·Granted Feb 21, 2012·15 cites·16 claims
- 0883US10387682B2Parallel access to running electronic design automation (EDA) applicationIBM·Filed 2017·Granted Aug 20, 2019·3 cites·15 claims
- 0983US8418107B2Performing statistical timing analysis with non-separable statistical and deterministic variationsHEMMETT JEFFREY G·Filed 2010·Granted Apr 9, 2013·7 cites·24 claims
- 1082US7788617B2Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysisIBM·Filed 2008·Granted Aug 31, 2010·12 cites·14 claims
- 1179US8560989B2Statistical clock cycle computationBUCK NATHAN·Filed 2011·Granted Oct 15, 2013·6 cites·20 claims
- 1278US7685549B2Method of constrained aggressor set selection for crosstalk induced noiseIBM·Filed 2007·Granted Mar 23, 2010·10 cites·24 claims
- 1377US11093675B1Statistical timing analysis considering multiple-input switchingIBM·Filed 2020·Granted Aug 17, 2021·1 cites·20 claims
- 1477US9836572B2Incremental common path pessimism analysisIBM·Filed 2015·Granted Dec 5, 2017·2 cites·17 claims
- 1576US11017137B2Efficient projection based adjustment evaluation in static timing analysis of integrated circuitsIBM·Filed 2019·Granted May 25, 2021·2 cites·15 claims
- 1676US8589842B1Device-based random variability modeling in timing analysisIBM·Filed 2012·Granted Nov 19, 2013·4 cites·20 claims
- 1775US10831954B1Technology lookup table-based default assertion generation and consumption for timing closure of VLSI designsIBM·Filed 2019·Granted Nov 10, 2020·2 cites·20 claims
- 1874US8458632B2Efficient slack projection for truncated distributionsFOREMAN ERIC A·Filed 2011·Granted Jun 4, 2013·4 cites·20 claims
- 1973US8732642B2Method for achieving an efficient statistical optimization of integrated circuitsVISWESWARIAH CHANDRAMOULI·Filed 2012·Granted May 20, 2014·3 cites·16 claims
- 2073US8141025B2Method of performing timing analysis on integrated circuit chips with consideration of process variationsSINHA DEBJIT·Filed 2009·Granted Mar 20, 2012·6 cites·17 claims
- 2171US9798843B2Statistical timing using macro-model considering statistical timing value entryIBM·Filed 2015·Granted Oct 24, 2017·2 cites·20 claims
- 2270US8103997B2Method of employing slew dependent pin capacitances to capture interconnect parasitics during timing abstraction of VLSI circuitsSINHA DEBJIT·Filed 2009·Granted Jan 24, 2012·6 cites·21 claims
- 2368US9940431B2Accurate statistical timing for boundary gates of hierarchical timing modelsIBM·Filed 2016·Granted Apr 10, 2018·1 cites·12 claims
- 2468US8122411B2Method of performing static timing analysis considering abstracted cell's interconnect parasiticsABBASPOUR SOROUSH·Filed 2009·Granted Feb 21, 2012·4 cites·16 claims
- 2564US9607124B2Method of hierarchical timing closure employing dynamic load-sensitive feedback constraintsIBM·Filed 2015·Granted Mar 28, 2017·1 cites·13 claims
- 2662US8930864B2Method of sharing and re-using timing models in a chip across multiple voltage domainsIBM·Filed 2012·Granted Jan 6, 2015·1 cites·19 claims
- 2760US10380289B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Aug 13, 2019·0 cites·9 claims
- 2859US10929567B2Parallel access to running electronic design automation (EDA) applicationIBM·Filed 2019·Granted Feb 23, 2021·0 cites·15 claims
- 2958US10380286B2Multi-sided variations for creating integrated circuitsIBM·Filed 2017·Granted Aug 13, 2019·0 cites·11 claims
- 3056US10169527B2Accurate statistical timing for boundary gates of hierarchical timing modelsIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 3156US2018357436A1Parallel access to running eda applicationIBM·Filed 2018·Application pending·0 cites
- 3255US10325059B2Incremental common path pessimism analysisIBM·Filed 2017·Granted Jun 18, 2019·0 cites·20 claims
- 3352US2024143885A1Multiply-Instantiated Block Modeling For Circuit Component Placement In Integrated CircuitGOOGLE LLC·Filed 2022·Application pending·0 cites
- 3450US8104005B2Method and apparatus for efficient incremental statistical timing analysis and optimizationSINHA DEBJIT·Filed 2008·Granted Jan 24, 2012·0 cites·24 claims
- 3547US10747925B1Variable accuracy incremental timing analysisIBM·Filed 2019·Granted Aug 18, 2020·0 cites·20 claims
- 3646US9916405B2Distributed timing analysis of a partitioned integrated circuit designIBM·Filed 2016·Granted Mar 13, 2018·0 cites·20 claims
- 3744US2014149956A1Corner specific normalization of static timing analysisIBM·Filed 2012·Application pending·0 cites
- 3842US9710594B2Variation-aware timing analysis using waveform constructionIBM·Filed 2015·Granted Jul 18, 2017·0 cites·18 claims
- 3941US9659121B1Deterministic and statistical timing modeling for differential circuitsIBM·Filed 2015·Granted May 23, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →