Inventor · disambiguated record
Dhulipalla Phaneendra Kumar
Also filed as: KUMAR DHULIPALLA PHANEENDRA
6 granted patents·1 pending application·8 citations·filing 2019–2025
71Inventor score
Files withST MICROELECTRONICS INT NV7
Top patents by PatentIndex Score
7 records- 0193US11442108B1Isolation logic test circuit and associated test methodST MICROELECTRONICS INT NV·Filed 2021·Granted Sep 13, 2022·4 cites·24 claims
- 0288US11513544B1Reset and safe state logic generation in dual power flow devicesST MICROELECTRONICS INT NV·Filed 2021·Granted Nov 29, 2022·4 cites·20 claims
- 0364US2025323809A1Controller area network extra-long (can-xl) low latency hardware and software partitioned architecture for message handlerST MICROELECTRONICS INT NV·Filed 2025·Application pending·0 cites
- 0460US11860993B2Dynamic randomization of password challengeST MICROELECTRONICS INT NV·Filed 2021·Granted Jan 2, 2024·0 cites·21 claims
- 0556US11227046B2Dynamic randomization of password challengeST MICROELECTRONICS INT NV·Filed 2019·Granted Jan 18, 2022·0 cites·18 claims
- 0647US11983025B2Reset and safe state logic generation in dual power flow devicesST MICROELECTRONICS INT NV·Filed 2022·Granted May 14, 2024·0 cites·20 claims
- 0747US11281795B2Hierarchical random scrambling of secure data storage resulting in randomness across chips and on power on resets of individual chipsST MICROELECTRONICS INT NV·Filed 2019·Granted Mar 22, 2022·0 cites·23 claims
Join the waitlist — get patent alerts
Get an alert when Dhulipalla Phaneendra Kumar files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →