Inventor · disambiguated record
Dinesh Gupta
Also filed as: GUPTA DINESH · GUPTA DINESH SAHEBLAL
15 granted patents·1 pending application·166 citations·filing 2005–2025
93Inventor score
Files withCADENCE DESIGN SYSTEMS INC4AMAZON TECH INC3GOLDMAN SACHS & CO LLC3BHARDWAJ VIVEK2TRANSWITCH CORP2
Top patents by PatentIndex Score
16 records- 0196US8365113B1Flow methodology for single pass parallel hierarchical timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Jan 29, 2013·51 cites·31 claims
- 0293US8640066B1Multi-phase models for timing closure of integrated circuit designsGUPTA DINESH·Filed 2010·Granted Jan 28, 2014·34 cites·25 claims
- 0391US8935642B1Methods for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Jan 13, 2015·13 cites·15 claims
- 0491US8539402B1Systems for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Sep 17, 2013·13 cites·5 claims
- 0588US12242468B1Generative machine learning with retriever having reconfigurable sequence of rankersGOLDMAN SACHS & CO LLC·Filed 2024·Granted Mar 4, 2025·10 cites·20 claims
- 0688US11550505B1Intra-shard parallelization of data stream processing using virtual shardsAMAZON TECH INC·Filed 2020·Granted Jan 10, 2023·4 cites·20 claims
- 0787US12321794B2Hybrid language model architecture for API orchestration including chain of thoughtGOLDMAN SACHS & CO LLC·Filed 2025·Granted Jun 3, 2025·2 cites·17 claims
- 0886US11968280B1Controlling ingestion of streaming data to serverless function executionsAMAZON TECH INC·Filed 2021·Granted Apr 23, 2024·3 cites·22 claims
- 0985US7926011B1System and method of generating hierarchical block-level timing constraints from chip-level timing constraintsCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 12, 2011·16 cites·25 claims
- 1084US9165098B1Machine readable products for single pass parallel hierarchical timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Oct 20, 2015·5 cites·10 claims
- 1183US11388210B1Streaming analytics using a serverless compute systemAMAZON TECH INC·Filed 2021·Granted Jul 12, 2022·2 cites·20 claims
- 1283US9152742B1Multi-phase models for timing closure of integrated circuit designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Oct 6, 2015·6 cites·21 claims
- 1370US8977994B1Circuit design system and method of generating hierarchical block-level timing constraints from chip-level timing constraintsLEVITSKY OLEG·Filed 2010·Granted Mar 10, 2015·4 cites·14 claims
- 1464US2025138907A1Hybrid language model architecture for api orchestration including chain of thoughtGOLDMAN SACHS & CO LLC·Filed 2024·Application pending·0 cites
- 1563US7558287B2Combined hardware and software implementation of link capacity adjustment scheme (LCAS) in SONET (synchronous optical network) virtual concatenation (VCAT)TRANSWITCH CORP·Filed 2005·Granted Jul 7, 2009·3 cites·12 claims
- 1638US7672315B2Methods and apparatus for deskewing VCAT/LCAS membersTRANSWITCH CORP·Filed 2005·Granted Mar 2, 2010·0 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →