Inventor · disambiguated record
Dimitri Kioussis
Also filed as: KIOUSSIS DIMITRI · KIOUSSIS DIMITRI R · KIOUSSIS DIMITRI ROBERT
13 granted patents·10 pending applications·650 citations·filing 2010–2023
91Inventor score
Top patents by PatentIndex Score
23 records- 0199US9305836B1Air gap semiconductor structure with selective cap bilayerIBM·Filed 2014·Granted Apr 5, 2016·488 cites·10 claims
- 0298US10043674B1Germanium etching systems and methodsAPPLIED MATERIALS INC·Filed 2017·Granted Aug 7, 2018·102 cites·20 claims
- 0396US10177227B1Method for fabricating junctions and spacers for horizontal gate all around devicesAPPLIED MATERIALS INC·Filed 2017·Granted Jan 8, 2019·40 cites·6 claims
- 0492US11694902B2Methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layersAPPLIED MATERIALS INC·Filed 2021·Granted Jul 4, 2023·2 cites·18 claims
- 0591US9711455B2Method of forming an air gap semiconductor structure with selective cap bilayerIBM·Filed 2015·Granted Jul 18, 2017·5 cites·12 claims
- 0689US10903054B2Multi-zone gas distribution systems and methodsAPPLIED MATERIALS INC·Filed 2017·Granted Jan 26, 2021·5 cites·20 claims
- 0788US9960117B2Air gap semiconductor structure with selective cap bilayerIBM·Filed 2015·Granted May 1, 2018·4 cites·18 claims
- 0884US11581165B2Multi-zone gas distribution systems and methodsAPPLIED MATERIALS INC·Filed 2021·Granted Feb 14, 2023·1 cites·20 claims
- 0977US12131913B2Methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layersAPPLIED MATERIALS INC·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 1076US12148597B2Multi-zone gas distribution systems and methodsAPPLIED MATERIALS INC·Filed 2023·Granted Nov 19, 2024·0 cites·19 claims
- 1175US11309404B2Integrated CMOS source drain formation with advanced controlAPPLIED MATERIALS INC·Filed 2019·Granted Apr 19, 2022·1 cites·14 claims
- 1269US2022199804A1Integrated CMOS Source Drain Formation With Advanced ControlAPPLIED MATERIALS INC·Filed 2022·Application pending·0 cites
- 1361US8183149B1Method of fabricating a conductive interconnect arrangement for a semiconductor devicePERMANA DAVID M·Filed 2010·Granted May 22, 2012·2 cites·18 claims
- 1459US10593553B2Germanium etching systems and methodsAPPLIED MATERIALS INC·Filed 2018·Granted Mar 17, 2020·0 cites·20 claims
- 1557US2025220986A1Airgap spacer wrapped around a contactINTEL CORP·Filed 2023·Application pending·0 cites
- 1653US2025220991A1Integrated circuit structure with direct backside source or drain contactINTEL CORP·Filed 2023·Application pending·0 cites
- 1751US2025218949A1Techniques to form integrated circuit structures with conductive interconnectsINTEL CORP·Filed 2023·Application pending·0 cites
- 1851US2025220967A1Integrated circuit structures having links for uniform grid metal gate and trench contact cutINTEL CORP·Filed 2023·Application pending·0 cites
- 1950US2025098230A1Integrated circuit structures having dual stress gatesINTEL CORP·Filed 2023·Application pending·0 cites
- 2049US2023033086A1Varying channel width in three-dimensional memory arrayINTEL CORP·Filed 2020·Application pending·0 cites
- 2148US2025221019A1Integrated circuit structures having uniform grid metal gate and trench contact plug with gate voltage threshold (vt) adjustmentINTEL CORP·Filed 2023·Application pending·0 cites
- 2242US2023395729A1Memory devices with gradient-doped control gate materialINTEL CORP·Filed 2020·Application pending·0 cites
- 2340US2014167265A1Methods of forming a bi-layer cap layer on copper-based conductive structures and devices with such a cap layerGLOBAL FOUNDRIES INC·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →