Inventor · disambiguated record
Dmitry Korchemny
Also filed as: KORCHEMNY DMITRY
8 granted patents·3 pending applications·19 citations·filing 2018–2023
80Inventor score
Files withSYNOPSYS INC11
Top patents by PatentIndex Score
11 records- 0193US11501050B1Analog mixed-signal assertion-based checker systemSYNOPSYS INC·Filed 2021·Granted Nov 15, 2022·8 cites·20 claims
- 0285US11544435B1On-the-fly computation of analog mixed-signal (AMS) measurementsSYNOPSYS INC·Filed 2021·Granted Jan 3, 2023·2 cites·20 claims
- 0381US11232174B1SAT solver based on interpretation and truth table analysisSYNOPSYS INC·Filed 2019·Granted Jan 25, 2022·5 cites·10 claims
- 0478US10962595B1Efficient realization of coverage collection in emulationSYNOPSYS INC·Filed 2018·Granted Mar 30, 2021·3 cites·25 claims
- 0561US11188695B2Unified functional coverage and synthesis flow for formal verification and emulationSYNOPSYS INC·Filed 2018·Granted Nov 30, 2021·1 cites·17 claims
- 0651US11176293B1Method and system for emulation clock tree reductionSYNOPSYS INC·Filed 2019·Granted Nov 16, 2021·0 cites·28 claims
- 0749US2023214574A1Extended regular expression matching in a directed acyclic graph by using assertion simulationSYNOPSYS INC·Filed 2022·Application pending·0 cites
- 0847US11386250B2Detecting timing violations in emulation using field programmable gate array (FPGA) reprogrammingSYNOPSYS INC·Filed 2021·Granted Jul 12, 2022·0 cites·20 claims
- 0942US2024273271A1Verifying nonoverlapping transactions described by assertions for sequential implicationsSYNOPSYS INC·Filed 2023·Application pending·0 cites
- 1038US10579760B2Force/release support in emulation and formal verificationSYNOPSYS INC·Filed 2018·Granted Mar 3, 2020·0 cites·22 claims
- 1138US2023017872A1Optimization of alternating büchi automata for formal verification of a circuit designSYNOPSYS INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →