Inventor · disambiguated record
Douglas B. Boyle
Also filed as: BOYLE DOUGLAS · BOYLE DOUGLAS B
34 granted patents·2 pending applications·3,244 citations·filing 1994–2015
98Inventor score
Files withLSI LOGIC CORP23MONTEREY DESIGN SYSTEMS INC5MONTEREY DESIGN SYSTEMS3BOYLE DOUGLAS B1PHOTONIC INT PTE LTD1
Top patents by PatentIndex Score
36 records- 0199US6557145B2Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 2001·Granted Apr 29, 2003·287 cites·24 claims
- 0297US5495419AIntegrated circuit physical design automation system utilizing optimization process decomposition and parallel processingLSI LOGIC CORP·Filed 1994·Granted Feb 27, 1996·199 cites·17 claims
- 0396US5761516ASingle chip multiprocessor architecture with internal task switching synchronization busLSI LOGIC CORP·Filed 1996·Granted Jun 2, 1998·297 cites·27 claims
- 0496US5636125AComputer implemented method for producing optimized cell placement for integrated circiut chipLSI LOGIC CORP·Filed 1995·Granted Jun 3, 1997·196 cites·17 claims
- 0595US9495295B1Photonics-optimized processor systemPHOTONIC INT PTE LTD·Filed 2015·Granted Nov 15, 2016·39 cites·16 claims
- 0694US5864854ASystem and method for maintaining a shared cache look-up tableLSI LOGIC CORP·Filed 1996·Granted Jan 26, 1999·243 cites·27 claims
- 0792US6155725ACell placement representation and transposition for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Dec 5, 2000·174 cites·24 claims
- 0892US5914887ACongestion based cost factor computing apparatus for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Jun 22, 1999·176 cites·27 claims
- 0991US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 1089US6092229ASingle chip systems using general purpose processorsLSI LOGIC CORP·Filed 1996·Granted Jul 18, 2000·152 cites·28 claims
- 1189US5557533ACell placement alteration apparatus for integrated circuit chip physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Sep 17, 1996·118 cites·37 claims
- 1288US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 1387US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 1485US6493658B1Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithmsLSI LOGIC CORP·Filed 1994·Granted Dec 10, 2002·104 cites·33 claims
- 1583US5903461AMethod of cell placement for an integrated circuit chip comprising chaotic placement and moving windowsLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·68 cites·40 claims
- 1683US5745363AOptimization processing for integrated circuit physical design automation system using optimally switched cost function computationsLSI LOGIC CORP·Filed 1996·Granted Apr 28, 1998·70 cites·23 claims
- 1781US5742510ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Apr 21, 1998·61 cites·28 claims
- 1880US5875117ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Feb 23, 1999·91 cites·32 claims
- 1979US5682322AOptimization processing for integrated circuit physical design automation system using chaotic fitness improvement methodLSI LOGIC CORP·Filed 1994·Granted Oct 28, 1997·76 cites·34 claims
- 2074US6118870AMicroprocessor having instruction set extensions for decryption and multimedia applicationsLSI LOGIC CORP·Filed 1996·Granted Sep 12, 2000·82 cites·23 claims
- 2169US5963975ASingle chip integrated circuit distributed shared memory (DSM) and communications nodesLSI LOGIC CORP·Filed 1997·Granted Oct 5, 1999·55 cites·26 claims
- 2269US5619419AMethod of cell placement for an itegrated circuit chip comprising integrated placement and cell overlap removalLSI LOGIC CORP·Filed 1994·Granted Apr 8, 1997·52 cites·42 claims
- 2368US5870313AOptimization processing for integrated circuit physical design automation system using parallel moving windowsLSI LOGIC CORP·Filed 1997·Granted Feb 9, 1999·49 cites·49 claims
- 2468US5781439AMethod for producing integrated circuit chip having optimized cell placementLSI LOGIC CORP·Filed 1995·Granted Jul 14, 1998·33 cites·17 claims
- 2567US5815403AFail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chipLSI LOGIC CORP·Filed 1994·Granted Sep 29, 1998·45 cites·8 claims
- 2667US5793644ACell placement alteration apparatus for integrated circuit chip physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Aug 11, 1998·44 cites·32 claims
- 2764US6099580AMethod for providing performance-driven logic optimization in an integrated circuit layout designMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Aug 8, 2000·44 cites·39 claims
- 2854US6367051B1System and method for concurrent buffer insertion and placement of logic gatesMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Apr 2, 2002·31 cites·23 claims
- 2953US8035139B2Dynamic random access memory having junction field effect transistor cell access deviceSUVOLTA INC·Filed 2008·Granted Oct 11, 2011·0 cites·5 claims
- 3051US5835378AComputer implemented method for leveling interconnect wiring density in a cell placement for an integrated circuit chipLSI LOGIC CORP·Filed 1995·Granted Nov 10, 1998·24 cites·30 claims
- 3149US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 3245US2005034087A1Method and apparatus for mapping platform-based design to multiple foundry processesFiled 2004·Application pending·0 cites
- 3341US2012009743A1Dynamic random access memory having junction field effect transistor cell access deviceBOYLE DOUGLAS B·Filed 2011·Application pending·0 cites
- 3439US6449756B1Method for accurate and efficient updates of timing information logic synthesis, placement and routing for integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Sep 10, 2002·13 cites·23 claims
- 3537US6385760B2System and method for concurrent placement of gates and associated wiringMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted May 7, 2002·9 cites·8 claims
- 3637US5517658AMethod for testing design timing parameters using a timing shell generatorLSI LOGIC CORP·Filed 1994·Granted May 14, 1996·16 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →