Inventor · disambiguated record
Donald Albert Evans
Also filed as: EVANS DONALD · EVANS DONALD A · EVANS DONALD ALBERT
45 granted patents·4 pending applications·437 citations·filing 1994–2014
98Inventor score
Top patents by PatentIndex Score
49 records- 0188US8923090B1Address decoding circuits for reducing address and memory enable setup timeLSI CORP·Filed 2013·Granted Dec 30, 2014·12 cites·21 claims
- 0284US8724421B2Dual rail power supply scheme for memoriesEVANS DONALD A·Filed 2012·Granted May 13, 2014·11 cites·21 claims
- 0375US7898887B2Sense amplifier with redundancyAGERE SYSTEMS INC·Filed 2007·Granted Mar 1, 2011·9 cites·20 claims
- 0474US8773927B2Adjusting bit-line discharge time in memory arrays based on characterized word-line delay and gate delayEVANS DONALD ALBERT·Filed 2012·Granted Jul 8, 2014·7 cites·16 claims
- 0573US7177212B2Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phaseAGERE SYSTEMS INC·Filed 2004·Granted Feb 13, 2007·16 cites·6 claims
- 0673US5793683AWordline and bitline redundancy with no performance penaltyIBM·Filed 1997·Granted Aug 11, 1998·34 cites·4 claims
- 0772US5996097ATesting logic associated with numerous memory cells in the word or bit dimension in parallelIBM·Filed 1997·Granted Nov 30, 1999·31 cites·14 claims
- 0871US9177635B1Dual rail single-ended read data paths for static random access memoriesLSI CORP·Filed 2014·Granted Nov 3, 2015·4 cites·11 claims
- 0971US5793592ADynamic dielectric protection circuit for a receiverIBM·Filed 1997·Granted Aug 11, 1998·25 cites·15 claims
- 1070US7848172B2Memory circuit having reduced power consumptionAGERE SYSTEMS INC·Filed 2008·Granted Dec 7, 2010·7 cites·20 claims
- 1166US6178134B1Static random access memory with global bit-linesLUCENT TECHNOLOGIES INC·Filed 1999·Granted Jan 23, 2001·26 cites·24 claims
- 1265US7301828B2Decoding techniques for read-only memoryAGERE SYSTEMS INC·Filed 2006·Granted Nov 27, 2007·3 cites·18 claims
- 1364US5929667AMethod and apparatus for protecting circuits subjected to high voltageIBM·Filed 1997·Granted Jul 27, 1999·19 cites·15 claims
- 1463US7826301B2Word line driver circuit with reduced leakageAGERE SYSTEMS INC·Filed 2007·Granted Nov 2, 2010·5 cites·20 claims
- 1563US7391633B2Accelerated searching for content-addressable memoryAGERE SYSTEMS INC·Filed 2006·Granted Jun 24, 2008·5 cites·21 claims
- 1662US8462562B1Memory device with area efficient power gating circuitryGOEL ANKUR·Filed 2011·Granted Jun 11, 2013·3 cites·20 claims
- 1761US7633830B2Reduced leakage driver circuit and memory device employing sameAGERE SYSTEMS INC·Filed 2007·Granted Dec 15, 2009·4 cites·22 claims
- 1861US7324364B2Layout techniques for memory circuitryAGERE SYSTEMS INC·Filed 2006·Granted Jan 29, 2008·2 cites·20 claims
- 1960US7042779B2Method and apparatus for reducing leakage current in a read only memory device using pre-charged sub-arraysAGERE SYSTEMS INC·Filed 2004·Granted May 9, 2006·10 cites·21 claims
- 2060US5793228ANoise-tolerant dynamic circuitsIBM·Filed 1997·Granted Aug 11, 1998·16 cites·8 claims
- 2159US5721957AMethod and system for storing data in cache and retrieving data from cache in a selected one of multiple data formatsIBM·Filed 1996·Granted Feb 24, 1998·42 cites·22 claims
- 2258US8125842B2Tracking circuit for reducing faults in a memoryDUDECK DENNIS E·Filed 2009·Granted Feb 28, 2012·4 cites·21 claims
- 2358US7755948B2Process and temperature tolerant non-volatile memoryAGERE SYSTEMS INC·Filed 2008·Granted Jul 13, 2010·3 cites·17 claims
- 2458US6046923AContent-addressable memory architecture with column muxingLUCENT TECHNOLOGIES INC·Filed 1999·Granted Apr 4, 2000·32 cites·13 claims
- 2557US8787099B2Adjusting access times to memory cells based on characterized word-line delay and gate delayEVANS DONALD ALBERT·Filed 2012·Granted Jul 22, 2014·2 cites·14 claims
- 2656US8610461B2Split decode latch with shared feedbackSTEPHANI RICHARD J·Filed 2011·Granted Dec 17, 2013·2 cites·20 claims
- 2756US8059472B2Process and temperature tolerant non-volatile memoryDUDECK DENNIS·Filed 2010·Granted Nov 15, 2011·2 cites·22 claims
- 2856US7551512B2Dual-port memoryAGERE SYSTEMS INC·Filed 2007·Granted Jun 23, 2009·3 cites·20 claims
- 2954US5638315AContent addressable memory for a data processing systemIBM·Filed 1995·Granted Jun 10, 1997·15 cites·20 claims
- 3053US5751648ATwo stage sensing for large static memory arraysIBM·Filed 1997·Granted May 12, 1998·14 cites·4 claims
- 3152US6879509B2Read-only memory architectureAGERE SYSTEMS INC·Filed 2003·Granted Apr 12, 2005·5 cites·67 claims
- 3251US8201032B2Generalized BIST for multiport memoriesEVANS DONALD A·Filed 2007·Granted Jun 12, 2012·2 cites·23 claims
- 3350US5592142AHigh speed greater than or equal to compare circuitIBM·Filed 1995·Granted Jan 7, 1997·24 cites·8 claims
- 3449US5815354AReceiver input voltage protection circuitIBM·Filed 1997·Granted Sep 29, 1998·16 cites·16 claims
- 3547US7558095B2Memory cell for content-addressable memoryAGERE SYSTEMS INC·Filed 2007·Granted Jul 7, 2009·1 cites·20 claims
- 3646US5715198AOutput latching circuit for static memory devicesIBM·Filed 1997·Granted Feb 3, 1998·10 cites·2 claims
- 3745US8365044B2Memory device with error correction based on automatic logic inversionAGERE SYSTEMS INC·Filed 2007·Granted Jan 29, 2013·1 cites·21 claims
- 3841US7460424B2Method and apparatus for reducing leakage current in a read only memory device using shortened precharge phaseAGERE SYSTEMS INC·Filed 2007·Granted Dec 2, 2008·0 cites·20 claims
- 3941US7085149B2Method and apparatus for reducing leakage current in a read only memory device using transistor biasAGERE SYSTEMS INC·Filed 2004·Granted Aug 1, 2006·2 cites·30 claims
- 4041US2013173944A1Reducing power consumption of memoryKOHLER ROSS·Filed 2011·Application pending·0 cites
- 4140US7363424B2Content addressable memories (CAMs) based on a binary CAM and having at least three statesAGERE SYSTEMS INC·Filed 2007·Granted Apr 22, 2008·0 cites·16 claims
- 4240US7191280B2Content addressable memories (CAMs) based on a binary CAM and having at least three statesAGERE SYSTEMS INC·Filed 2003·Granted Mar 13, 2007·2 cites·15 claims
- 4338US8284622B2Memory device with phase distribution circuit for controlling relative durations of precharge and active phasesEVANS DONALD ALBERT·Filed 2010·Granted Oct 9, 2012·0 cites·20 claims
- 4438US7933155B2Memory device with reduced buffer current during power-down modeAGERE SYSTEMS INC·Filed 2007·Granted Apr 26, 2011·0 cites·20 claims
- 4537US6353903B1Method and apparatus for testing differential signalsIBM·Filed 1994·Granted Mar 5, 2002·6 cites·11 claims
- 4637US2015138864A1Memory architecture with alternating segments and multiple bitlinesLSI CORP·Filed 2013·Application pending·0 cites
- 4737US2015138863A1Interleaved write assist for hierarchical bitline sram architecturesLSI CORP·Filed 2013·Application pending·0 cites
- 4836US7433254B2Accelerated single-ended sensing for a memory circuitAGERE SYSTEMS INC·Filed 2006·Granted Oct 7, 2008·0 cites·22 claims
- 4933US2006090106A1Generalized BIST for multiport memoriesEVANS DONALD A·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →