Generalized BIST for multiport memories

Abstract

A generalized hardware architecture that supports built-in self testing (BIST) for a range of different computer memory configurations and a generalized BIST algorithm can be compiled, based on specified configuration characteristics (e.g., the number of write ports, the number of read ports, the number of entries, and the number of bits per entry in the computer memory), to generate the hardware design for a particular computer memory system. In one embodiment, the generalized hardware architecture includes a multiplexer block that enables a single BIST comparator to be multiplexed for use in performing BIST testing via different read ports of the computer memory.

1 . BIST circuitry for testing a memory having multiple read ports, the BIST circuitry comprising: 
 a multiplexer block adapted to receive data from each of the multiple read ports and output selected data from one of the multiple read ports; and    a comparator adapted to compare the selected data from the multiplexer block with expected data to determine whether the selected data matches the expected data.    
   
   
       2 . The invention of  claim 1 , further comprising a controller adapted to generate and update a mux select signal to cause the multiplexer block to sequentially select data from different ones of the multiple read ports.  
   
   
       3 . The invention of  claim 2 , wherein: 
 the mux select signal comprises multiple bits; and    further comprising a mux decoder adapted to convert the multi-bit mux select signal for use in controlling the multiplexer block.    
   
   
       4 . The invention of the  claim 1 , wherein the BIST circuitry has only one comparator.  
   
   
       5 . The invention of  claim 1 , wherein the BIST circuitry is adapted to test different types of memory having different numbers of read ports by appropriately controlling the selection of data by the multiplexer block.  
   
   
       6 . A method for designing BIST circuitry for testing a memory having one or more write ports and one or more read ports, the method comprising: 
 assigning one or more values for one or more memory configuration parameters for the memory; and    compiling a generic BIST algorithm based on the one or more memory configuration parameters to generate a design for the BIST circuitry.    
   
   
       7 . The invention of  claim 6 , wherein the compiling is implemented using a computer-implemented design tool.  
   
   
       8 . The invention of  claim 6 , wherein the one or more memory configuration parameters comprise a number of write ports for the memory and a number of read ports for the memory.  
   
   
       9 . The invention of  claim 8 , wherein the total number of write and read ports is limited to a specified value.  
   
   
       10 . The invention of  claim 8 , wherein the one or more memory configuration parameters further comprises a number of bits per memory entry and a number of entries in the memory.  
   
   
       11 . The invention of  claim 6 , wherein the generic BIST algorithm is adapted to be compiled based on different sets of the memory configuration parameter values to generate different BIST circuitry designs corresponding to different memory configurations.  
   
   
       12 . The invention of  claim 11 , wherein: 
 the one or more memory configuration parameters comprise a number of write ports for the memory and a number of read ports for the memory; and    the total number of write and read ports is limited to a specified value.    
   
   
       13 . The invention of  claim 6 , wherein the generic BIST algorithm is adapted to test memory cells in the memory, one or more read port decoders for the memory, and one or more write port decoders for the memory.  
   
   
       14 . The invention of  claim 13 , wherein the generic BIST algorithm is further adapted to test bit-write enabling for the memory and a comparator of the BIST circuitry.  
   
   
       15 . The invention of  claim 14 , the generic BIST algorithm comprises: 
 a first test phase adapted to test the memory cells and the one or more read port decoders;    a second test phase adapted to test the one or more write port decoders; and    a third test phase adapted to test the bit-write enabling and the comparator.    
   
   
       16 . The invention of  claim 13 , wherein: 
 the memory has two or more write ports and two or more write port decoders; and    testing for the write port decoders involves cycling through the different write port decoders.    
   
   
       17 . The invention of  claim 13 , wherein: 
 the memory has two or more read ports and two or more read port decoders; and    testing for the read port decoders involves cycling through the different read port decoders.    
   
   
       18 . The invention of  claim 6 , wherein: 
 the memory has multiple read ports; and    the design for the BIST circuitry comprises: 
 a multiplexer block adapted to receive data from each of the multiple read ports and output selected data from one of the multiple read ports; and  
 a comparator adapted to compare the selected data from the multiplexer block with expected data to determine whether the selected data matches the expected data.  
   
   
   
       19 . The invention of  claim 18 , wherein the design further comprises a controller adapted to generate and update a mux select signal to cause the multiplexer block to sequentially select data from different ones of the multiple read ports.  
   
   
       20 . A computer-implemented design tool for designing BIST circuitry for testing a memory having one or more write ports and one or more read ports, the design tool comprising: 
 means for assigning one or more values for one or more memory configuration parameters for the memory; and    means for compiling a generic BIST algorithm based on the one or more memory configuration parameters to generate a design for the BIST circuitry.