Inventor · disambiguated record
Dongzi Liu
Also filed as: LIU DONGZI
5 granted patents·52 citations·filing 2007–2016
78Inventor score
Technology areasG06F
Top patents by PatentIndex Score
5 records- 0189US9026978B1Reverse interface logic model for optimizing physical hierarchy under full chip constraintCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 5, 2015·32 cites·20 claims
- 0283US9639644B1Method and apparatus for master-clone optimization during circuit analysisCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted May 2, 2017·5 cites·21 claims
- 0379US9141740B2Methods, systems, and articles of manufacture for implementing full-chip optimization with reduced physical design dataLIU DONGZI·Filed 2011·Granted Sep 22, 2015·9 cites·36 claims
- 0474US9652582B1Multi-instantiated block timing optimizationCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 0567US7930675B2Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysisCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Apr 19, 2011·4 cites·25 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →