Inventor · disambiguated record
Dominik Metzler
Also filed as: METZLER DOMINIK
25 granted patents·40 citations·filing 2014–2022
92Inventor score
Top patents by PatentIndex Score
25 records- 0197US11923246B2Via CD controllable top via structureIBM·Filed 2021·Granted Mar 5, 2024·4 cites·10 claims
- 0297US10534276B1Lithographic photomask alignment using non-planar alignment structures formed on waferIBM·Filed 2019·Granted Jan 14, 2020·11 cites·16 claims
- 0395US11223008B2Pillar-based memory hardmask smoothing and stress reductionIBM·Filed 2019·Granted Jan 11, 2022·6 cites·6 claims
- 0492US10685879B1Lithographic alignment of a conductive line to a viaIBM·Filed 2019·Granted Jun 16, 2020·8 cites·19 claims
- 0588US9620382B2Reactor for plasma-based atomic layer etching of materialsUNIV MARYLAND·Filed 2014·Granted Apr 11, 2017·9 cites·17 claims
- 0678US11227892B2MRAM integration with BEOL interconnect including top viaIBM·Filed 2019·Granted Jan 18, 2022·2 cites·16 claims
- 0773US11812668B2Pillar-based memory hardmask smoothing and stress reductionIBM·Filed 2021·Granted Nov 7, 2023·0 cites·20 claims
- 0869US12243771B2Selective patterning of vias with hardmasksIBM·Filed 2022·Granted Mar 4, 2025·0 cites·19 claims
- 0969US11830807B2Placing top vias at line ends by selective growth of via mask from line cut dielectricIBM·Filed 2021·Granted Nov 28, 2023·0 cites·6 claims
- 1061US11688636B2Spin on scaffold film for forming topviaIBM·Filed 2021·Granted Jun 27, 2023·0 cites·20 claims
- 1159US12020949B2Subtractive patterning of interconnect structuresIBM·Filed 2021·Granted Jun 25, 2024·0 cites·20 claims
- 1259US11189561B2Placing top vias at line ends by selective growth of via mask from line cut dielectricIBM·Filed 2019·Granted Nov 30, 2021·0 cites·18 claims
- 1358US11276607B2Selective patterning of vias with hardmasksIBM·Filed 2019·Granted Mar 15, 2022·0 cites·16 claims
- 1455US12261044B2Multi-layer hardmask for defect reduction in EUV patterningLAM RES CORP·Filed 2021·Granted Mar 25, 2025·0 cites·21 claims
- 1554US12277960B2Modified top electrode contact for MRAM embedding in advanced logic nodesIBM·Filed 2021·Granted Apr 15, 2025·0 cites·7 claims
- 1654US11244907B2Metal surface preparation for increased alignment contrastIBM·Filed 2020·Granted Feb 8, 2022·0 cites·19 claims
- 1754US11094590B1Structurally stable self-aligned subtractive viasIBM·Filed 2020·Granted Aug 17, 2021·0 cites·20 claims
- 1853US11404317B2Method for fabricating a semiconductor device including self-aligned top via formation at line endsIBM·Filed 2019·Granted Aug 2, 2022·0 cites·24 claims
- 1953US11133260B2Self-aligned top viaIBM·Filed 2019·Granted Sep 28, 2021·0 cites·16 claims
- 2051US12237175B2Polymerization protective liner for reactive ion etch in patterningLAM RES CORP·Filed 2020·Granted Feb 25, 2025·0 cites·20 claims
- 2151US11189527B2Self-aligned top vias over metal lines formed by a damascene processIBM·Filed 2020·Granted Nov 30, 2021·0 cites·20 claims
- 2248US11152261B2Self-aligned top via formation at line endsIBM·Filed 2019·Granted Oct 19, 2021·0 cites·24 claims
- 2347US11205678B2Embedded MRAM device with top viaIBM·Filed 2020·Granted Dec 21, 2021·0 cites·20 claims
- 2446US11189783B2Embedded MRAM device formation with self-aligned dielectric capIBM·Filed 2019·Granted Nov 30, 2021·0 cites·14 claims
- 2546US10879190B2Patterning integration scheme with trench alignment marksIBM·Filed 2019·Granted Dec 29, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →