Inventor · disambiguated record
Doron Orenstein
Also filed as: ORENSTEIN DORON
30 granted patents·4 pending applications·701 citations·filing 1993–2018
97Inventor score
Top patents by PatentIndex Score
34 records- 0196US8914613B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bitsSPERBER ZEEV·Filed 2011·Granted Dec 16, 2014·22 cites·27 claims
- 0296US7437581B2Method and apparatus for varying energy per instruction according to the amount of available parallelismINTEL CORP·Filed 2004·Granted Oct 14, 2008·138 cites·50 claims
- 0395US9672034B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a same set of per-lane control bitsINTEL CORP·Filed 2013·Granted Jun 6, 2017·17 cites·21 claims
- 0494US6557083B1Memory system for multiple data typesINTEL CORP·Filed 2000·Granted Apr 29, 2003·102 cites·10 claims
- 0593US8078836B2Vector shuffle instructions operating on multiple lanes each having a plurality of data elements using a common set of per-lane control bitsSPERBER ZEEV·Filed 2007·Granted Dec 13, 2011·21 cites·37 claims
- 0687US6944720B2Memory system for multiple data typesINTEL CORP·Filed 2003·Granted Sep 13, 2005·46 cites·5 claims
- 0786US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 0886US6580427B1Z-compression mechanismINTEL CORP·Filed 2000·Granted Jun 17, 2003·43 cites·23 claims
- 0984US8281109B2Compressed instruction formatVALENTINE ROBERT·Filed 2007·Granted Oct 2, 2012·8 cites·30 claims
- 1083US5835748AMethod for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register fileINTEL CORP·Filed 1995·Granted Nov 10, 1998·114 cites·157 claims
- 1179US8078831B2Method and apparatus for affinity-guided speculative helper threads in chip multiprocessorsWANG HONG·Filed 2010·Granted Dec 13, 2011·5 cites·8 claims
- 1278US7721129B2Method and apparatus for reducing clock frequency during low workload periodsINTEL CORP·Filed 2006·Granted May 18, 2010·8 cites·11 claims
- 1376US6886105B2Method and apparatus for resuming memory operations from a low latency wake-up low power stateINTEL CORP·Filed 2000·Granted Apr 26, 2005·23 cites·31 claims
- 1475US7051227B2Method and apparatus for reducing clock frequency during low workload periodsINTEL CORP·Filed 2002·Granted May 23, 2006·23 cites·13 claims
- 1575US5450605ABoundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructionsINTEL CORP·Filed 1993·Granted Sep 12, 1995·60 cites·5 claims
- 1672US9086872B2Unpacking packed data in multiple lanesHARGIL ASAF·Filed 2009·Granted Jul 21, 2015·8 cites·31 claims
- 1772US6724391B1Mechanism for implementing Z-compression transparentlyINTEL CORP·Filed 2000·Granted Apr 20, 2004·21 cites·18 claims
- 1867US11048507B2Compressed instruction formatINTEL CORP·Filed 2018·Granted Jun 29, 2021·0 cites·19 claims
- 1965US10831477B2In-lane vector shuffle instructionsINTEL CORP·Filed 2017·Granted Nov 10, 2020·0 cites·18 claims
- 2065US10514918B2In-lane vector shuffle instructionsINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·27 claims
- 2165US10509652B2In-lane vector shuffle instructionsINTEL CORP·Filed 2017·Granted Dec 17, 2019·0 cites·27 claims
- 2264US10514916B2In-lane vector shuffle instructionsINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·22 claims
- 2364US10514917B2In-lane vector shuffle instructionsINTEL CORP·Filed 2017·Granted Dec 24, 2019·0 cites·27 claims
- 2462US10095515B2Compressed instruction formatINTEL CORP·Filed 2017·Granted Oct 9, 2018·0 cites·18 claims
- 2561US9081562B2Unpacking packed data in multiple lanesINTEL CORP·Filed 2013·Granted Jul 14, 2015·1 cites·17 claims
- 2657US9569208B2Compressed instruction formatVALENTINE ROBERT·Filed 2014·Granted Feb 14, 2017·0 cites·3 claims
- 2757US9235415B2Permute operations with flexible zero controlINTEL CORP·Filed 2014·Granted Jan 12, 2016·0 cites·20 claims
- 2856US8756403B2Compressed instruction formatINTEL CORP·Filed 2013·Granted Jun 17, 2014·0 cites·28 claims
- 2951US7844801B2Method and apparatus for affinity-guided speculative helper threads in chip multiprocessorsINTEL CORP·Filed 2003·Granted Nov 30, 2010·2 cites·32 claims
- 3048US5787026AMethod and apparatus for providing memory access in a processor pipelineINTEL CORP·Filed 1995·Granted Jul 28, 1998·21 cites·35 claims
- 3147US2006149931A1Runahead execution in a central processing unitHAITHAM AKKARY·Filed 2004·Application pending·0 cites
- 3244US2014095847A1Instruction and highly efficient micro-architecture to enable instant context switch for user-level threadingORENSTEIN DORON·Filed 2012·Application pending·0 cites
- 3340US2016011874A1Silent memory instructions and miss-rate tracking to optimize switching policy on threads in a processing deviceORENSTEIN DORON·Filed 2014·Application pending·0 cites
- 3439US2004003215A1Method and apparatus for executing low power validations for high confidence speculationsFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →