Inventor · disambiguated record
Donald W. Plass
Also filed as: PLASS DONALD · PLASS DONALD W · PLASS DONALD WAYNE
56 granted patents·9 pending applications·319 citations·filing 1988–2019
98Inventor score
Top patents by PatentIndex Score
65 records- 0191US8120968B2High voltage word line driverREOHR WILLIAM ROBERT·Filed 2010·Granted Feb 21, 2012·17 cites·22 claims
- 0291US7064990B1Method and apparatus for implementing multiple column redundancy for memoryIBM·Filed 2005·Granted Jun 20, 2006·29 cites·17 claims
- 0389US7437626B2Efficient method of test and soft repair of SRAM with redundancyIBM·Filed 2005·Granted Oct 14, 2008·21 cites·3 claims
- 0485US7088638B1Global and local read control synchronization method and system for a memory array configured with multiple memory subarraysIBM·Filed 2005·Granted Aug 8, 2006·17 cites·26 claims
- 0585US7075855B1Memory output timing control circuit with merged functionsIBM·Filed 2005·Granted Jul 11, 2006·16 cites·18 claims
- 0683US7471590B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2007·Granted Dec 30, 2008·11 cites·5 claims
- 0782US10943647B1Bit-line mux driver with diode header for computer memoryIBM·Filed 2019·Granted Mar 9, 2021·5 cites·20 claims
- 0882US8472271B2Systems and methods for memory device prechargingDAWSON JAMES W·Filed 2011·Granted Jun 25, 2013·10 cites·25 claims
- 0982US7953987B2Protection of secure electronic modules against attacksIBM·Filed 2007·Granted May 31, 2011·13 cites·20 claims
- 1080US7793173B2Efficient memory product for test and soft repair of SRAM with redundancyIBM·Filed 2008·Granted Sep 7, 2010·11 cites·3 claims
- 1178US7176725B2Fast pulse powered NOR decode apparatus for semiconductor devicesIBM·Filed 2005·Granted Feb 13, 2007·9 cites·19 claims
- 1276US7283417B2Write control circuitry and method for a memory array configured with multiple memory subarraysIBM·Filed 2005·Granted Oct 16, 2007·8 cites·14 claims
- 1373US10930339B1Voltage bitline high (VBLH) regulation for computer memoryIBM·Filed 2019·Granted Feb 23, 2021·3 cites·20 claims
- 1473US7606060B2Eight transistor SRAM cell with improved stability requiring only one word lineIBM·Filed 2007·Granted Oct 20, 2009·7 cites·2 claims
- 1573US7295458B2Eight transistor SRAM cell with improved stability requiring only one word lineIBM·Filed 2006·Granted Nov 13, 2007·7 cites·11 claims
- 1673US7085173B1Write driver circuit for memory arrayIBM·Filed 2005·Granted Aug 1, 2006·8 cites·12 claims
- 1772US7787284B2Integrated circuit chip with improved array stabilityIBM·Filed 2008·Granted Aug 31, 2010·5 cites·20 claims
- 1871US8605528B2Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methodsBARTH JR JOHN E·Filed 2011·Granted Dec 10, 2013·5 cites·20 claims
- 1970US7099206B2High density bitline selection apparatus for semiconductor memory devicesIBM·Filed 2005·Granted Aug 29, 2006·7 cites·21 claims
- 2069US7219275B2Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancyIBM·Filed 2005·Granted May 15, 2007·7 cites·16 claims
- 2167US10559346B2Bias-controlled bit-line sensing scheme for eDRAMIBM·Filed 2018·Granted Feb 11, 2020·2 cites·15 claims
- 2267US9250271B2Charge pump generator with direct voltage sensorIBM·Filed 2013·Granted Feb 2, 2016·2 cites·16 claims
- 2367US6737685B2Compact SRAM cell layout for implementing one-port or two-port operationIBM·Filed 2002·Granted May 18, 2004·21 cites·16 claims
- 2466US9224437B2Gated-feedback sense amplifier for single-ended local bit-line memoriesGLOBALFOUNDRIES INC·Filed 2013·Granted Dec 29, 2015·3 cites·20 claims
- 2563US9025403B1Dynamic cascode-managed high-voltage word-line driver circuitIBM·Filed 2013·Granted May 5, 2015·2 cites·13 claims
- 2663US7233542B2Method and apparatus for address generationIBM·Filed 2005·Granted Jun 19, 2007·5 cites·8 claims
- 2762US9263096B1Voltage comparator circuit and usage thereofIBM·Filed 2014·Granted Feb 16, 2016·2 cites·11 claims
- 2861US10832756B1Negative voltage generation for computer memoryIBM·Filed 2019·Granted Nov 10, 2020·1 cites·20 claims
- 2960US7173875B2SRAM array with improved cell stabilityIBM·Filed 2004·Granted Feb 6, 2007·10 cites·38 claims
- 3060US6728912B2SOI cell stability test methodIBM·Filed 2001·Granted Apr 27, 2004·11 cites·4 claims
- 3158US7068554B1Apparatus and method for implementing multiple memory redundancy with delay tracking clockIBM·Filed 2005·Granted Jun 27, 2006·4 cites·17 claims
- 3256US9341655B2Charge pump generator with direct voltage sensorGLOBALFOUNDRIES INC·Filed 2014·Granted May 17, 2016·0 cites·8 claims
- 3356US7688650B2Write control method for a memory array configured with multiple memory subarraysIBM·Filed 2008·Granted Mar 30, 2010·2 cites·5 claims
- 3455US7102944B1Programmable analog control of a bitline evaluation circuitIBM·Filed 2005·Granted Sep 5, 2006·3 cites·1 claims
- 3553US7299374B2Clock control method and apparatus for a memory arrayIBM·Filed 2005·Granted Nov 20, 2007·2 cites·20 claims
- 3652US7023759B1System and method for synchronizing memory array signalsIBM·Filed 2005·Granted Apr 4, 2006·2 cites·19 claims
- 3751US8214592B2Dynamic runtime modification of array layout for offsetARIMILLI RAVI K·Filed 2009·Granted Jul 3, 2012·0 cites·19 claims
- 3851US2008028255A1Clock control method and apparatus for a memory arrayIBM·Filed 2007·Application pending·0 cites
- 3950US7170320B2Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steeringIBM·Filed 2005·Granted Jan 30, 2007·1 cites·19 claims
- 4050US6584023B1System for implementing a column redundancy scheme for arrays with controls that span multiple data bitsIBM·Filed 2002·Granted Jun 24, 2003·6 cites·9 claims
- 4149US7009895B2Method for skip over redundancy decode with very low overheadIBM·Filed 2004·Granted Mar 7, 2006·5 cites·10 claims
- 4247US9748958B2Dynamic high voltage driver with adjustable clamped output levelIBM·Filed 2016·Granted Aug 29, 2017·0 cites·20 claims
- 4347US7380191B2ABIST data compression and serialization for memory built-in self test of SRAM with redundancyIBM·Filed 2005·Granted May 27, 2008·1 cites·6 claims
- 4446US4901279AMESFET sram with power saving current-limiting transistorsIBM·Filed 1988·Granted Feb 13, 1990·9 cites·7 claims
- 4545US10762953B2Memory array with reduced circuitryIBM·Filed 2018·Granted Sep 1, 2020·0 cites·20 claims
- 4645US9053770B1Dynamic cascode-managed high-voltage word-line driver circuitIBM·Filed 2014·Granted Jun 9, 2015·0 cites·7 claims
- 4745US7210084B2Integrated system logic and ABIST data compression for an SRAM directoryIBM·Filed 2003·Granted Apr 24, 2007·4 cites·5 claims
- 4843US7403412B2Integrated circuit chip with improved array stabilityIBM·Filed 2007·Granted Jul 22, 2008·0 cites·12 claims
- 4943US7295457B2Integrated circuit chip with improved array stabilityIBM·Filed 2004·Granted Nov 13, 2007·2 cites·8 claims
- 5043US6822885B2High speed latch and compare functionIBM·Filed 2003·Granted Nov 23, 2004·3 cites·12 claims
Showing the top 50 of 65 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →