Inventor · disambiguated record
Doug Weiser
Also filed as: WEISER DOUG
13 granted patents·2 pending applications·57 citations·filing 2003–2023
86Inventor score
Top patents by PatentIndex Score
15 records- 0188US7039888B2Modeling process for integrated circuit film resistorsTEXAS INSTRUMENTS INC·Filed 2003·Granted May 2, 2006·52 cites·14 claims
- 0273US10522663B2Integrated JFET structure with implanted backgateTEXAS INSTRUMENTS INC·Filed 2018·Granted Dec 31, 2019·1 cites·20 claims
- 0369US11676993B2Method and structure for dual sheet resistance trimmable thin film resistorsTEXAS INSTRUMENTS INC·Filed 2020·Granted Jun 13, 2023·0 cites·24 claims
- 0461US11257907B2High voltage demos transistor with improved threshold voltage matchingTEXAS INSTRUMENTS INC·Filed 2020·Granted Feb 22, 2022·0 cites·18 claims
- 0560US8436635B2Semiconductor wafer having test modules including pin matrix selectable test devicesMOLLAT MARTIN B·Filed 2009·Granted May 7, 2013·4 cites·10 claims
- 0658US10770538B2Method and structure for dual sheet resistance trimmable thin film resistorsTEXAS INSTRUMENTS INC·Filed 2018·Granted Sep 8, 2020·0 cites·21 claims
- 0754US10079294B2Integrated JFET structure with implanted backgateTEXAS INSTRUMENTS INC·Filed 2016·Granted Sep 18, 2018·0 cites·20 claims
- 0854US2024405125A1Buried channel semiconductor device including energy barrier modulation region(s)TEXAS INSTRUMENTS INC·Filed 2023·Application pending·0 cites
- 0953US10629683B2High voltage DEMOS transistor with improved threshold voltage matchingTEXAS INSTRUMENTS INC·Filed 2017·Granted Apr 21, 2020·0 cites·20 claims
- 1053US9991329B2Method and structure for dual sheet resistance trimmable thin film resistors at same levelTEXAS INSTRUMENTS INC·Filed 2016·Granted Jun 5, 2018·0 cites·12 claims
- 1147US10103278B2Silicon IMPATT diodeTEXAS INSTRUMENTS INC·Filed 2016·Granted Oct 16, 2018·0 cites·19 claims
- 1247US9412879B2Integration of the silicon IMPATT diode in an analog technologyTEXAS INSTRUMENTS INC·Filed 2014·Granted Aug 9, 2016·0 cites·8 claims
- 1346US10497630B2High density wafer level test moduleTEXAS INSTRUMENTS INC·Filed 2018·Granted Dec 3, 2019·0 cites·17 claims
- 1446US10374100B2Programmable non-volatile memory with low off currentTEXAS INSTRUMENTS INC·Filed 2017·Granted Aug 6, 2019·0 cites·20 claims
- 1543US2025081449A1Asymmetrical channel floating gate three-state one-time programmable nonvolatile memoryTEXAS INSTRUMENTS INC·Filed 2023·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Doug Weiser files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →