Inventor · disambiguated record
Edward C. King
Also filed as: KING EDWARD · KING EDWARD C
27 granted patents·517 citations·filing 1983–2011
97Inventor score
Top patents by PatentIndex Score
27 records- 0183US5581731AMethod and apparatus for managing video data for faster access by selectively caching video dataFiled 1994·Granted Dec 3, 1996·58 cites·15 claims
- 0282US4966458AOptical system for a multidetector array spectrographMILTON ROY CO·Filed 1989·Granted Oct 30, 1990·60 cites·4 claims
- 0378US4507888AMagnetic digital display signKING DESIGN INC·Filed 1983·Granted Apr 2, 1985·38 cites·15 claims
- 0473US8839001B2Infinite key memory transaction unitKING EDWARD C·Filed 2011·Granted Sep 16, 2014·4 cites·17 claims
- 0572US5530941ASystem and method for prefetching data from a main computer memory into a cache memoryNCR CORP·Filed 1990·Granted Jun 25, 1996·53 cites·13 claims
- 0669US4583312AChangeable sign board with magnetic charactersKING DESIGN INC·Filed 1983·Granted Apr 22, 1986·31 cites·15 claims
- 0760US7630875B2Automatic time warp for electronic system simulationCPU TECHNOLOGY INC·Filed 2005·Granted Dec 8, 2009·4 cites·16 claims
- 0855US5761455ADynamic bus reconfiguration logicCPU TECHNOLOGY INC·Filed 1995·Granted Jun 2, 1998·31 cites·15 claims
- 0954US4875773AOptical system for a multidetector array spectrographMILTON ROY CO·Filed 1988·Granted Oct 24, 1989·17 cites·32 claims
- 1053US5499376AHigh speed mask and logical combination operations for parallel processor unitsCPU TECHNOLOGY INC·Filed 1993·Granted Mar 12, 1996·22 cites·10 claims
- 1151US5852564AMethod and apparatus for interactively displaying signal information during computer simulation of an electrical circuitCPU TECHNOLOGY INC·Filed 1996·Granted Dec 22, 1998·22 cites·15 claims
- 1250US5848276AHigh speed, direct register access operation for parallel processing unitsCPU TECHNOLOGY INC·Filed 1995·Granted Dec 8, 1998·24 cites·5 claims
- 1347US5420994AMethod for reading a multiple byte data element in a memory system with at least one cache and a main memoryNCR CORP·Filed 1990·Granted May 30, 1995·21 cites·15 claims
- 1446US5615356AMethod and apparatus for interactively displaying signal information during computer simulation of an electrical circuitCPU TECHNOLOGY INC·Filed 1994·Granted Mar 25, 1997·15 cites·7 claims
- 1544US5699529AWork station or similar data processing system including interfacing means to a data channelNCR CORP·Filed 1991·Granted Dec 16, 1997·22 cites·19 claims
- 1643US5751994ASystem and method for enhancing computer operation by prefetching data elements on a common bus without delaying bus access by multiple bus mastersNCR CORP·Filed 1997·Granted May 12, 1998·14 cites·5 claims
- 1741US5630098ASystem and method for interleaving memory addresses between memory banks based on the capacity of the memory banksNCR CORP·Filed 1991·Granted May 13, 1997·13 cites·11 claims
- 1839US5440754AWork station and method for transferring data between an external bus and a memory unitNCR CORP·Filed 1991·Granted Aug 8, 1995·12 cites·17 claims
- 1938US5410656AWork station interfacing means having burst mode capabilityNCR CORP·Filed 1991·Granted Apr 25, 1995·11 cites·12 claims
- 2037US5835945AMemory system with write buffer, prefetch and internal cachesNCR CORP·Filed 1990·Granted Nov 10, 1998·10 cites·23 claims
- 2134US5604883AComputer memory open page bias method and systemNCR CORP·Filed 1996·Granted Feb 18, 1997·7 cites·16 claims
- 2233US5953740AComputer memory system having programmable operational characteristics based on characteristics of a central processorNCR CORP·Filed 1993·Granted Sep 14, 1999·7 cites·9 claims
- 2333US5640536AWork station architecture with selectable CPUNCR CORP·Filed 1991·Granted Jun 17, 1997·6 cites·18 claims
- 2433US5363492AInternal bus for work station interfacing meansNCR CO·Filed 1991·Granted Nov 8, 1994·6 cites·13 claims
- 2529US5652907AHigh speed mask and logical combination operations for parallel processor unitsCPU TECHNOLOGY INC·Filed 1995·Granted Jul 29, 1997·0 cites·10 claims
- 2628US5832253AMultiprocessors system for selectively wire-oring a combination of signal lines and thereafter using one line to control the running or stalling of a selected processorCPU TECHNOLOGY INC·Filed 1993·Granted Nov 3, 1998·5 cites·20 claims
- 2724US5428751AWork station including a direct memory access controller and interfacing means to a data channelNCR CORP·Filed 1991·Granted Jun 27, 1995·4 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →