Inventor · disambiguated record
Edward Law
Also filed as: LAW EDWARD · LAW EDWARD L T · LAW EDWARD LAP ZAK
22 granted patents·11 pending applications·296 citations·filing 2001–2019
95Inventor score
Files withBROADCOM CORP14AVAGO TECH INT SALES PTE LID3AVAGO TECHNOLOGIES GENERAL IP2HU KEVIN KUNZHONG2HU KUNZHONG KEVIN2
Top patents by PatentIndex Score
33 records- 0196US6882042B2Thermally and electrically enhanced ball grid array packagingBROADCOM CORP·Filed 2001·Granted Apr 19, 2005·86 cites·23 claims
- 0294US8367475B2Chip scale package assembly in reconstitution panel process formatBROADCOM CORP·Filed 2011·Granted Feb 5, 2013·31 cites·20 claims
- 0393US10008439B2Thin recon interposer package without TSV for fine input/output pitch fan-outAVAGO TECHNOLOGIES GENERAL IP·Filed 2016·Granted Jun 26, 2018·10 cites·20 claims
- 0492US7259445B2Thermal enhanced package for block mold assemblyADVANCED INTERCONNECT TECH LTD·Filed 2003·Granted Aug 21, 2007·101 cites·13 claims
- 0591US8686558B2Thermally and electrically enhanced ball grid array packageZHAO SAM ZIQUN·Filed 2011·Granted Apr 1, 2014·9 cites·20 claims
- 0684US10615110B2Thin recon interposer package without TSV for fine input/output pitch fan-outAVAGO TECH INT SALES PTE LID·Filed 2018·Granted Apr 7, 2020·3 cites·20 claims
- 0784US8922014B2Wafer level semiconductor packageBROADCOM CORP·Filed 2013·Granted Dec 30, 2014·5 cites·22 claims
- 0884US8587123B2Multi-chip and multi-substrate reconstitution based packagingLAW EDWARD·Filed 2011·Granted Nov 19, 2013·9 cites·20 claims
- 0983US8957694B2Wafer level package resistance monitor schemeHU KUNZHONG·Filed 2012·Granted Feb 17, 2015·7 cites·18 claims
- 1077US9693461B2Magnetic-core three-dimensional (3D) inductors and packaging integrationBROADCOM CORP·Filed 2015·Granted Jun 27, 2017·3 cites·24 claims
- 1174US9390993B2Semiconductor border protection sealantBROADCOM CORP·Filed 2014·Granted Jul 12, 2016·3 cites·31 claims
- 1270US8779598B2Method and apparatuses for integrated circuit substrate manufactureYEUNG FAN·Filed 2011·Granted Jul 15, 2014·5 cites·20 claims
- 1370US8169067B2Low profile ball grid array (BGA) package with exposed die and method of making sameLAW EDWARD·Filed 2006·Granted May 1, 2012·5 cites·14 claims
- 1469US9564391B2Thermal enhanced package using embedded substrateHU KEVIN (KUNZHONG)·Filed 2011·Granted Feb 7, 2017·3 cites·20 claims
- 1569US8592259B2Method of fabricating a wafer level semiconductor package having a pre-formed dielectric layerHU KEVIN KUNZHONG·Filed 2011·Granted Nov 26, 2013·2 cites·20 claims
- 1669US8039949B2Ball grid array package having one or more stiffenersBROADCOM CORP·Filed 2009·Granted Oct 18, 2011·2 cites·25 claims
- 1762US7629681B2Ball grid array package with patterned stiffener surface and method of assembling the sameBROADCOM CORP·Filed 2004·Granted Dec 8, 2009·6 cites·8 claims
- 1859US11049829B2Redistribution metal and under bump metal interconnect structures and methodAVAGO TECH INT SALES PTE LID·Filed 2019·Granted Jun 29, 2021·0 cites·20 claims
- 1957US2014210083A1Thermally and electrically enhanced ball grid array packageBROADCOM CORP·Filed 2014·Application pending·0 cites
- 2055US8945991B2Fabricating a wafer level semiconductor package having a pre-formed dielectric layerBROADCOM CORP·Filed 2013·Granted Feb 3, 2015·0 cites·25 claims
- 2154US7091469B2Packaging for optoelectronic devicesST ASSEMBLY TEST SERVICES LTD·Filed 2004·Granted Aug 15, 2006·6 cites·20 claims
- 2254US2015340308A1Reconstituted interposer semiconductor packageBROADCOM CORP·Filed 2014·Application pending·0 cites
- 2353US2018233440A1Reconstituted interposer semiconductor packageAVAGO TECHNOLOGIES GENERAL IP·Filed 2018·Application pending·0 cites
- 2452US10504862B2Redistribution metal and under bump metal interconnect structures and methodAVAGO TECH INT SALES PTE LID·Filed 2017·Granted Dec 10, 2019·0 cites·20 claims
- 2545US2009194872A1Depopulating integrated circuit package ball locations to enable improved edge clearance in shipping trayBROADCOM CORP·Filed 2008·Application pending·0 cites
- 2645US2015303172A1Reconstitution techniques for semiconductor packagesBROADCOM CORP·Filed 2014·Application pending·0 cites
- 2745US2011115074A1Wafer bumping using printed under bump metalizationBROADCOM CORP·Filed 2010·Application pending·0 cites
- 2843US2007273023A1Integrated circuit package having exposed thermally conducting bodyBROADCOM CORP·Filed 2006·Application pending·0 cites
- 2941US2012241951A1Wafer bumping using printed under bump metalizationHU KUNZHONG KEVIN·Filed 2012·Application pending·0 cites
- 3040US2007065984A1Thermal enhanced package for block mold assemblyLAU DANIEL K·Filed 2006·Application pending·0 cites
- 3139US2012187545A1Direct through via wafer level fanout packageKHAN REZAUR RAHMAN·Filed 2011·Application pending·0 cites
- 3237US2012299187A1Aluminum Bond Pad With Trench Thinning for Fine Pitch Ultra-Thick Aluminum ProductsOERTLE KENT CHARLES·Filed 2011·Application pending·0 cites
- 3331US8088647B2Bumping free flip chip processHU KUNZHONG KEVIN·Filed 2010·Granted Jan 3, 2012·0 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when Edward Law files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →