Inventor · disambiguated record
Edoardo Prete
Also filed as: PRETE EDOARDO
24 granted patents·8 pending applications·69 citations·filing 2002–2024
93Inventor score
Files withADVANCED MICRO DEVICES INC13INFINEON TECHNOLOGIES AG6QIMONDA AG4PRETE EDOARDO2SANDERS ANTHONY F2
Top patents by PatentIndex Score
32 records- 0193US9673849B1Common mode extraction and tracking for data signalingADVANCED MICRO DEVICES INC·Filed 2016·Granted Jun 6, 2017·15 cites·12 claims
- 0288US8760946B2Method and apparatus for memory access delay trainingDEARTH GLENN A·Filed 2012·Granted Jun 24, 2014·12 cites·29 claims
- 0387US11805026B2Channel training using a replica laneADVANCED MICRO DEVICES INC·Filed 2020·Granted Oct 31, 2023·2 cites·20 claims
- 0485US9639495B2Integrated controller for training memory physical layer interfaceADVANCED MICRO DEVICES INC·Filed 2014·Granted May 2, 2017·8 cites·19 claims
- 0577US9183125B2DDR receiver enable cycle trainingBRANDL KEVIN M·Filed 2011·Granted Nov 10, 2015·5 cites·24 claims
- 0675US7721130B2Apparatus and method for switching an apparatus to a power saving modeQIMONDA AG·Filed 2006·Granted May 18, 2010·8 cites·33 claims
- 0774US10749756B2Channel training using a replica laneADVANCED MICRO DEVICES INC·Filed 2016·Granted Aug 18, 2020·2 cites·18 claims
- 0872US7620136B2Clock and data recovery circuit having gain controlINFINEON TECHNOLOGIES AG·Filed 2006·Granted Nov 17, 2009·5 cites·24 claims
- 0970US8782458B2System and method of data communications between electronic devicesNYGREN AARON·Filed 2011·Granted Jul 15, 2014·3 cites·32 claims
- 1060US12174769B2Periodic receiver clock data recovery with dynamic data edgeADVANCED MICRO DEVICES INC·Filed 2022·Granted Dec 24, 2024·0 cites·20 claims
- 1159US12388490B2Receiver equalization circuitry using variable termination and T-coilADVANCED MICRO DEVICES INC·Filed 2022·Granted Aug 12, 2025·0 cites·20 claims
- 1259US12034440B2Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed linksADVANCED MICRO DEVICES INC·Filed 2021·Granted Jul 9, 2024·0 cites·20 claims
- 1358US2025007516A1Combination scheme for baseline wander, direct current level shifting, and receiver linear equalization for high speed linksADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 1457US10692545B2Low power VTT generation mechanism for receiver terminationADVANCED MICRO DEVICES INC·Filed 2018·Granted Jun 23, 2020·1 cites·20 claims
- 1556US8553754B2Method and apparatus for using DFE in a system with non-continuous dataMANGASER RAMON·Filed 2010·Granted Oct 8, 2013·2 cites·27 claims
- 1655US2025103424A1Circuit element link training in a memory deviceADVANCED MICRO DEVICES INC·Filed 2024·Application pending·0 cites
- 1754US11860685B2Clock frequency divider circuitADVANCED MICRO DEVICES INC·Filed 2021·Granted Jan 2, 2024·0 cites·20 claims
- 1846US7936201B2Apparatus and method for providing a signal for transmission via a signal lineQIMONDA AG·Filed 2006·Granted May 3, 2011·0 cites·28 claims
- 1945US7733815B2Data sampler including a first stage and a second stageQIMONDA AG·Filed 2006·Granted Jun 8, 2010·1 cites·21 claims
- 2045US7420430B2Method and arrangement for generating an output clock signal with an adjustable phase relation from a plurality of input clock signalsINFINEON TECHNOLOGIES AG·Filed 2005·Granted Sep 2, 2008·1 cites·19 claims
- 2144US2014325105A1Memory system components for split channel architectureADVANCED MICRO DEVICES INC·Filed 2013·Application pending·0 cites
- 2241US2008123792A1Apparatus and method for transmitting signals over a signal linePRETE EDOARDO·Filed 2006·Application pending·0 cites
- 2339US7532695B2Clock signal extraction device and method for extracting a clock signal from data signalINFINEON TECHNOLOGIES AG·Filed 2002·Granted May 12, 2009·2 cites·20 claims
- 2438US10103837B2Asynchronous feedback trainingADVANCED MICRO DEVICES INC·Filed 2016·Granted Oct 16, 2018·0 cites·14 claims
- 2537US6836162B2Method and arrangement for frequency doublingINFINEON TECHNOLOGIES AG·Filed 2003·Granted Dec 28, 2004·0 cites·15 claims
- 2636US7405591B2Concept for interfacing a first circuit requiring a first supply voltage and a second supply circuit requiring a second supply voltageQIMONDA AG·Filed 2006·Granted Jul 29, 2008·0 cites·33 claims
- 2735US7313211B2Method and apparatus for phase detectionINFINEON TECHNOLOGIES AG·Filed 2003·Granted Dec 25, 2007·0 cites·31 claims
- 2834US7782927B2Generating a transmission clock signal and a reception clock signal for a transceiver using an oscillatorLANTIQ DEUTSCHLAND GMBH·Filed 2004·Granted Aug 24, 2010·2 cites·2 claims
- 2934US2007183552A1Clock and data recovery circuit including first and second stagesSANDERS ANTHONY F·Filed 2006·Application pending·0 cites
- 3034US2007177702A1Receiving data over channels with intersymbol interferenceSANDERS ANTHONY F·Filed 2006·Application pending·0 cites
- 3133US2007288716A1Memory system with a retiming circuit and a method of exchanging data and timing signals between a memory controller and a memory deviceINFINEON TECHNOLOGIES AG·Filed 2006·Application pending·0 cites
- 3232US2008126624A1Memory buffer and method for buffering dataPRETE EDOARDO·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →