Clock frequency divider circuit

Abstract

A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.

What is claimed is: 
     
       1. An apparatus comprising:
 a first clock divider circuit configured to:
 receive a first input clock signal; and 
 generate a first output clock signal based on the first input clock signal; and 
 
 a second clock divider circuit configured to:
 receive a second input clock signal, wherein the first input clock signal and the second input clock signal have an initial phase difference between them; 
 receive a first intermediate clock signal based on the first output clock signal; 
 receive a reset signal that is asserted asynchronously, in a given clock cycle of the second input clock signal, with respect to the second input clock signal; and 
 in response to assertion of the reset signal, generate, in the given clock cycle, a second output clock signal such that the first output clock signal and the second output clock signal have the initial phase difference between them. 
 
 
     
     
       2. The apparatus as recited in  claim 1 , wherein a first input frequency of the first input clock signal is equal to a second input frequency of the second input clock signal. 
     
     
       3. The apparatus as recited in  claim 1 , further comprising a sequential element comprising circuitry configured to:
 receive the first output clock signal as a data input signal; 
 receive the second input clock signal; and 
 generate the first intermediate clock signal to convey to the second clock divider circuit. 
 
     
     
       4. The apparatus as recited in  claim 1 , wherein the second clock divider circuit comprises a multiplexer circuit configured to:
 receive the reset signal, in the given clock cycle, as a select input signal; and 
 generate, in the given clock cycle, a second intermediate clock signal. 
 
     
     
       5. The apparatus as recited in  claim 4 , wherein the multiplexer circuit comprises:
 a first pass gate circuit configured to:
 receive an inverted version of the second output clock signal as a first data input signal; and 
 convey, in the given clock cycle, a non-inverted version of the second output clock signal as the second intermediate clock signal, responsive to the reset signal being negated; and 
 
 a second pass gate circuit configured to:
 receive the first intermediate clock signal as a second data input signal; and 
 convey, in the given clock cycle, an inverted version of the first intermediate clock signal as the second intermediate clock signal, responsive to assertion of the reset signal. 
 
 
     
     
       6. The apparatus as recited in  claim 5 , wherein the second clock divider circuit comprises a sequential element comprising circuitry configured to:
 receive the second intermediate clock signal as a data input signal; 
 receive the second input clock signal; and 
 generate the second output clock signal. 
 
     
     
       7. The apparatus as recited in  claim 6 , wherein the sequential element of the second clock divider circuit comprises a third pass gate circuit configured to receive the second intermediate clock signal from one of the first pass gate circuit and the second pass gate circuit of the multiplexer circuit. 
     
     
       8. A method comprising:
 receiving, by a first clock divider circuit, a first input clock signal; 
 generating, by the first clock divider circuit, a first output clock signal based on the first input clock signal; 
 receiving, by a second clock divider circuit, a second input clock signal, wherein the first input clock signal and the second input clock signal have an initial phase difference between them; 
 receiving, by the second clock divider circuit, a first intermediate clock signal based on the first output clock signal; 
 receiving, by the second clock divider circuit, a reset signal that is asserted asynchronously, in a given clock cycle of the second input clock signal, with respect to the second input clock signal; and 
 in response to the reset signal being asserted, generating, in the given clock cycle by the second clock divider circuit, a second output clock signal such that the first output clock signal and the second output clock signal have the initial phase difference between them. 
 
     
     
       9. The method as recited in  claim 8 , wherein a first input frequency of the first input clock signal is equal to a second input frequency of the second input clock signal. 
     
     
       10. The method as recited in  claim 8 , further comprising:
 receiving, by a sequential element circuit, the first output clock signal as a data input signal; 
 receiving, by the sequential element circuit, the second input clock signal; and 
 generating, by the sequential element circuit, the first intermediate clock signal to convey to the second clock divider circuit. 
 
     
     
       11. The method as recited in  claim 8 , further comprising:
 receiving, by a multiplexer circuit of the second clock divider circuit, the reset signal, in the given clock cycle, as a select input signal; and 
 generating, in the given clock cycle by the multiplexer circuit, a second intermediate clock signal. 
 
     
     
       12. The method as recited in  claim 11 , further comprising:
 receiving, by a first pass gate circuit of the multiplexer circuit, an inverted version of the second output clock signal as a first data input signal; 
 conveying, in the given clock cycle by the first pass gate circuit of the multiplexer circuit, a non-inverted version of the second output clock signal as the second intermediate clock signal, responsive to the reset signal being negated; 
 receiving, by a second pass gate circuit of the multiplexer circuit, the first intermediate clock signal as a second data input signal; and 
 conveying, in the given clock cycle by the second pass gate circuit of the multiplexer circuit, an inverted version of the first intermediate clock signal as the second intermediate clock signal, responsive to the reset signal being asserted. 
 
     
     
       13. The method as recited in  claim 12 , further comprising:
 receiving, by a sequential element circuit of the second clock divider circuit, the second intermediate clock signal as a data input signal; 
 receiving, by the sequential element circuit, the second input clock signal; and 
 generating, by the sequential element circuit, the second output clock signal. 
 
     
     
       14. The method as recited in  claim 13 , further comprising receiving, by a third pass gate circuit of the sequential element circuit, the second intermediate clock signal from one of the first pass gate circuit and the second pass gate circuit of the multiplexer circuit. 
     
     
       15. A computing system comprising:
 a memory configured to store instructions of one or more tasks and source data to be processed by the one or more tasks; 
 an integrated circuit configured to execute the instructions using the source data, wherein the integrated circuit comprises one or more clock frequency dividers, each comprising:
 a first clock divider circuit configured to:
 receive a first input clock signal; and 
 generate a first output clock signal based on the first input clock signal; and 
 
 a second clock divider circuit configured to:
 receive a second input clock signal, wherein the first input clock signal and the second input clock signal have an initial phase difference between them; 
 receive a first intermediate clock signal based on the first output clock signal; 
 receive a reset signal that is asserted asynchronously, in a given clock cycle of the second input clock signal, with respect to the second input clock signal; and 
 in response to assertion of the reset signal, generate, in the given clock cycle, a second output clock signal such that the first output clock signal and the second output clock signal have the initial phase difference between them. 
 
 
 
     
     
       16. The computing system as recited in  claim 15 , wherein a given clock frequency divider circuit of the one or more clock frequency dividers comprises a sequential element circuit configured to:
 receive the first output clock signal as a data input signal; 
 receive the second input clock signal; and 
 generate the first intermediate clock signal to convey to the second clock divider circuit. 
 
     
     
       17. The computing system as recited in  claim 15 , wherein the second clock divider circuit comprises a multiplexer circuit configured to:
 receive the reset signal, in the given clock cycle, as a select input signal; and 
 generate, in the given clock cycle, a second intermediate clock signal. 
 
     
     
       18. The computing system as recited in  claim 17 , wherein the multiplexer circuit comprises:
 a first pass gate circuit configured to:
 receive an inverted version of the second output clock signal as a first data input signal; and 
 convey, in the given clock cycle, a non-inverted version of the second output clock signal as the second intermediate clock signal, responsive to the reset signal being negated; and 
 
 a second pass gate circuit configured to:
 receive the first intermediate clock signal as a second data input signal; and 
 convey, in the given clock cycle, an inverted version of the first intermediate clock signal as the second intermediate clock signal, responsive to the reset signal being asserted. 
 
 
     
     
       19. The computing system as recited in  claim 18 , wherein the second clock divider circuit comprises a sequential element circuit configured to:
 receive the second intermediate clock signal as a data input signal; 
 receive the second input clock signal; and 
 generate the second output clock signal. 
 
     
     
       20. The computing system as recited in  claim 19 , wherein the sequential element circuit of the second clock divider circuit comprises a third pass gate circuit configured to receive the second intermediate clock signal from one of the first pass gate circuit and the second pass gate circuit of the multiplexer circuit.