Inventor · disambiguated record
Ekaterina M. Ambroladze
Also filed as: AMBROLADZE EKATERINA M
47 granted patents·3 pending applications·86 citations·filing 2008–2024
97Inventor score
Top patents by PatentIndex Score
50 records- 0189US8364899B2User-controlled targeted cache purgeIBM·Filed 2010·Granted Jan 29, 2013·13 cites·17 claims
- 0288US10055355B1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Aug 21, 2018·4 cites·1 claims
- 0388US9104583B2On demand allocation of cache buffer slotsAMBROLADZE EKATERINA M·Filed 2010·Granted Aug 11, 2015·13 cites·20 claims
- 0487US9507660B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Nov 29, 2016·4 cites·1 claims
- 0585US9898407B2Configuration based cache coherency protocol selectionIBM·Filed 2015·Granted Feb 20, 2018·3 cites·11 claims
- 0683US9703661B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2015·Granted Jul 11, 2017·3 cites·14 claims
- 0783US9244851B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexIBM·Filed 2013·Granted Jan 26, 2016·6 cites·6 claims
- 0880US9858190B2Maintaining order with parallel access data streamsIBM·Filed 2015·Granted Jan 2, 2018·3 cites·12 claims
- 0980US9594689B2Designated cache data backup during system operationIBM·Filed 2015·Granted Mar 14, 2017·3 cites·17 claims
- 1079US8447905B2Dynamic multi-level cache including resource access fairness schemeAMBROLADZE EKATERINA M·Filed 2010·Granted May 21, 2013·6 cites·15 claims
- 1178US10649908B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Granted May 12, 2020·1 cites·17 claims
- 1277US10915461B2Multilevel cache eviction managementIBM·Filed 2019·Granted Feb 9, 2021·2 cites·14 claims
- 1377US10042554B2Increased bandwidth of ordered stores in a non-uniform memory subsystemIBM·Filed 2015·Granted Aug 7, 2018·2 cites·7 claims
- 1475US10437729B2Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2017·Granted Oct 8, 2019·1 cites·12 claims
- 1571US10528253B2Increased bandwidth of ordered stores in a non-uniform memory subsystemIBM·Filed 2014·Granted Jan 7, 2020·2 cites·13 claims
- 1671US9678848B2Eliminate corrupted portions of cache during runtimeIBM·Filed 2016·Granted Jun 13, 2017·1 cites·1 claims
- 1771US8250243B2Diagnostic data collection and storage put-away station in a multiprocessor systemBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Aug 21, 2012·3 cites·27 claims
- 1869US8595570B1Bitline deletionAMBROLADZE EKATERINA M·Filed 2012·Granted Nov 26, 2013·2 cites·21 claims
- 1969US8250308B2Cache coherency protocol with built in avoidance for conflicting responsesPAPAZOVA VESSELINA K·Filed 2008·Granted Aug 21, 2012·7 cites·19 claims
- 2068US9003125B2Cache coherency protocol for allowing parallel data fetches and eviction to the same addressable indexAMBROLADZE EKATERINA M·Filed 2012·Granted Apr 7, 2015·2 cites·11 claims
- 2165US10824565B2Configuration based cache coherency protocol selectionIBM·Filed 2019·Granted Nov 3, 2020·0 cites·20 claims
- 2265US8874957B2Dynamic cache correction mechanism to allow constant access to addressable indexIBM·Filed 2013·Granted Oct 28, 2014·1 cites·8 claims
- 2365US8645796B2Dynamic pipeline cache error correctionAMBROLADZE EKATERINA M·Filed 2010·Granted Feb 4, 2014·2 cites·20 claims
- 2464US12050538B2Castout handling in a distributed cache topologyIBM·Filed 2022·Granted Jul 30, 2024·0 cites·20 claims
- 2564US2019251036A1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Application pending·0 cites
- 2664US2019251037A1Non-disruptive clearing of varying address ranges from cacheIBM·Filed 2019·Application pending·0 cites
- 2762US10402328B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Sep 3, 2019·0 cites·20 claims
- 2862US10394712B2Configuration based cache coherency protocol selectionIBM·Filed 2018·Granted Aug 27, 2019·0 cites·20 claims
- 2960US9886382B2Configuration based cache coherency protocol selectionIBM·Filed 2014·Granted Feb 6, 2018·0 cites·20 claims
- 3059US8468536B2Multiple level linked LRU priorityBERGER DEANNA POSTLES DUNN·Filed 2010·Granted Jun 18, 2013·1 cites·15 claims
- 3158US12475079B1Bidirectional ring-based interconnection networks having a cross bar for multiprocessorsIBM·Filed 2024·Granted Nov 18, 2025·0 cites·20 claims
- 3258US10529396B2Preinstall of partial store cache linesIBM·Filed 2017·Granted Jan 7, 2020·1 cites·20 claims
- 3358US10169260B2Multiprocessor cache buffer managementIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 3456US9298468B2Monitoring processing time in a shared pipelineIBM·Filed 2013·Granted Mar 29, 2016·0 cites·20 claims
- 3555US11042483B2Efficient eviction of whole set associated cache or selected range of addressesIBM·Filed 2019·Granted Jun 22, 2021·0 cites·20 claims
- 3652US9086990B2Bitline deletionIBM·Filed 2013·Granted Jul 21, 2015·0 cites·14 claims
- 3752US8719618B2Dynamic cache correction mechanism to allow constant access to addressable indexAMBROLADZE EKATERINA M·Filed 2012·Granted May 6, 2014·0 cites·12 claims
- 3851US8788891B2Bitline deletionAMBROLADZE EKATERINA M·Filed 2012·Granted Jul 22, 2014·0 cites·8 claims
- 3951US2024061803A1Serialized broadcast command messaging in a distributed symmetric multiprocessing (smp) systemIBM·Filed 2022·Application pending·0 cites
- 4050US12332783B2Input/output (I/O) store protocol for pipelining coherent operationsIBM·Filed 2022·Granted Jun 17, 2025·0 cites·18 claims
- 4150US9892067B2Multiprocessor cache buffer managementIBM·Filed 2015·Granted Feb 13, 2018·0 cites·17 claims
- 4249US10901902B2Efficient inclusive cache managementIBM·Filed 2019·Granted Jan 26, 2021·0 cites·13 claims
- 4349US8671267B2Monitoring processing time in a shared pipelineAMBROLADZE EKATERINA M·Filed 2010·Granted Mar 11, 2014·0 cites·20 claims
- 4446US10831661B2Coherent cache with simultaneous data requests in same addressable indexIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 4546US10380020B2Achieving high bandwidth on ordered direct memory access write stream into a processor cacheIBM·Filed 2017·Granted Aug 13, 2019·0 cites·17 claims
- 4646US8327070B2Method for optimizing sequential data fetches in a computer systemAMBROLADZE EKATERINA M·Filed 2010·Granted Dec 4, 2012·0 cites·20 claims
- 4744US8522076B2Error detection and recovery in a shared pipelineAMBROLADZE EKATERINA M·Filed 2010·Granted Aug 27, 2013·0 cites·20 claims
- 4841US8392621B2Managing dataflow in a temporary memoryAMBROLADZE EKATERINA M·Filed 2010·Granted Mar 5, 2013·0 cites·20 claims
- 4938US8365055B2High performance cache directory error correction codeIBM·Filed 2010·Granted Jan 29, 2013·0 cites·20 claims
- 5037US10169272B2Data processing apparatus and methodIBM·Filed 2015·Granted Jan 1, 2019·0 cites·18 claims
Join the waitlist — get patent alerts
Get an alert when Ekaterina M. Ambroladze files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →