Non-disruptive clearing of varying address ranges from cache

Abstract

In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

What is claimed is: 
     
         1 . A computer program product for purging an address range from a cache, the computer program product comprising:
 one or more non-transitory computer readable storage media and program instructions stored on the one or more non-transitory computer readable storage media, the program instructions comprising:
 program instructions to quiesce a computing system; 
 program instructions to issue a command to purge storage addresses from a cache to higher level memory, wherein:
 the command comprises a starting storage address, a range of storage addresses to be purged, an indication that the purge is a non-quiesce selective purge, and a multiplier, and 
 the range of storage addresses to be purged is based on the multiplier; 
 
 responsive to each cache of the computing system activating the command, wherein activating the command comprises causing the storage addresses from the cache to be inaccessible to operations attempting to access the storage addresses from the cache, program instructions to end the quiesce of the computing system; 
 subsequent to ending the quiesce of the computing system, program instructions to purge storage addresses from the cache, based on the command, to the higher level memory; 
 concurrent to purging the storage addresses from the cache, program instructions to identify an attempt to access a first storage address within the range of storage addresses to be purged from the cache; 
 responsive to the attempt, program instructions to generate an invalid address response; and 
   
       program instructions to update a configuration array with a location of the purged storage addresses within the higher level memory.