Inventor · disambiguated record
Eric G. Liniger
Also filed as: LINIGER ERIC G · LINIGER ERIC GERHARD
31 granted patents·3 pending applications·1,549 citations·filing 1997–2023
98Inventor score
Top patents by PatentIndex Score
34 records- 0199US10418277B2Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2018·Granted Sep 17, 2019·159 cites·20 claims
- 0299US9892961B1Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2016·Granted Feb 13, 2018·49 cites·13 claims
- 0397US6734090B2Method of making an edge seal for a semiconductor deviceIBM·Filed 2002·Granted May 11, 2004·605 cites·9 claims
- 0497US6271102B1Method and system for dicing wafers, and semiconductor structures incorporating the products thereofIBM·Filed 1998·Granted Aug 7, 2001·125 cites·11 claims
- 0596US10115629B2Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2017·Granted Oct 30, 2018·8 cites·8 claims
- 0694US7247946B2On-chip Cu interconnection using 1 to 5 nm thick metal capIBM·Filed 2005·Granted Jul 24, 2007·35 cites·14 claims
- 0794US6022791AChip crack stopIBM·Filed 1997·Granted Feb 8, 2000·222 cites·15 claims
- 0891US6455443B1Method of fabricating low-dielectric constant interlevel dielectric films for BEOL interconnects with enhanced adhesion and low-defect densityIBM·Filed 2001·Granted Sep 24, 2002·60 cites·22 claims
- 0989US7265437B2Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical propertiesSONY CORP·Filed 2005·Granted Sep 4, 2007·14 cites·16 claims
- 1088US7357977B2Ultralow dielectric constant layer with controlled biaxial stressIBM·Filed 2005·Granted Apr 15, 2008·10 cites·7 claims
- 1186US11658062B2Air gap spacer formation for nano-scale semiconductor devicesTESSERA LLC·Filed 2019·Granted May 23, 2023·2 cites·27 claims
- 1285US12224203B2Air gap spacer formation for nano-scale semiconductor devicesADEIA SEMICONDUCTOR SOLUTIONS LLC·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 1383US9281211B2Nanoscale interconnect structureIBM·Filed 2014·Granted Mar 8, 2016·5 cites·11 claims
- 1483US6915795B2Method and system for dicing wafers, and semiconductor structures incorporating the products thereofIBM·Filed 2003·Granted Jul 12, 2005·20 cites·11 claims
- 1580US7491578B1Method of forming crack trapping and arrest in thin film structuresIBM·Filed 2008·Granted Feb 17, 2009·8 cites·1 claims
- 1680US7163883B2Edge seal for a semiconductor deviceIBM·Filed 2003·Granted Jan 16, 2007·27 cites·6 claims
- 1779US10309884B2Predicting semiconductor package warpageIBM·Filed 2017·Granted Jun 4, 2019·1 cites·20 claims
- 1878US9018089B2Multiple step anneal method and semiconductor formed by multiple step annealLINIGER ERIC G·Filed 2011·Granted Apr 28, 2015·6 cites·21 claims
- 1978US7517790B2Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modificationIBM·Filed 2005·Granted Apr 14, 2009·7 cites·16 claims
- 2074US7573130B1Crack trapping and arrest in thin film structuresIBM·Filed 2009·Granted Aug 11, 2009·5 cites·1 claims
- 2171US5953627AProcess for manufacture of integrated circuit deviceIBM·Filed 1997·Granted Sep 14, 1999·40 cites·8 claims
- 2270US6177360B1Process for manufacture of integrated circuit deviceIBM·Filed 1997·Granted Jan 23, 2001·39 cites·17 claims
- 2366US9613900B2Nanoscale interconnect structureIBM·Filed 2016·Granted Apr 4, 2017·1 cites·15 claims
- 2465US6636290B1Methods of forming liquid display panels and the like wherein using two-component epoxy sealantIBM·Filed 1999·Granted Oct 21, 2003·32 cites·11 claims
- 2563US6600213B2Semiconductor structure and package including a chip having chamfered edgesIBM·Filed 2001·Granted Jul 29, 2003·7 cites·8 claims
- 2663US5888838AMethod and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation informationIBM·Filed 1998·Granted Mar 30, 1999·25 cites·17 claims
- 2760US6222145B1Mechanical strength die sortingIBM·Filed 1998·Granted Apr 24, 2001·22 cites·25 claims
- 2858US2009304951A1Ultralow dielectric constant layer with controlled biaxial stressIBM·Filed 2009·Application pending·0 cites
- 2955US2008286494A1Ultralow dielectric constant layer with controlled biaxial stressIBM·Filed 2008·Application pending·0 cites
- 3054US9772268B2Predicting semiconductor package warpageIBM·Filed 2015·Granted Sep 26, 2017·0 cites·11 claims
- 3153US7998880B2Low k dielectric CVD film formation process with in-situ imbedded nanolayers to improve mechanical propertiesIBM·Filed 2007·Granted Aug 16, 2011·0 cites·11 claims
- 3251US6171873B1Method and apparatus for preventing chip breakage during semiconductor manufacturing using wafer grinding striation informationIBM·Filed 1998·Granted Jan 9, 2001·15 cites·5 claims
- 3350US2008079176A1Method and structure to enhance temperature/humidity/bias performance of semiconductor devices by surface modificationIBM·Filed 2007·Application pending·0 cites
- 3447US7678673B2Strengthening of a structure by infiltrationIBM·Filed 2007·Granted Mar 16, 2010·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →