Inventor · disambiguated record
Eric Sprangle
Also filed as: SPRANGLE ERIC · SPRANGLE ERIC A · SPRANGLE ERIC S
24 granted patents·4 pending applications·290 citations·filing 2002–2020
96Inventor score
Top patents by PatentIndex Score
28 records- 0197US8683183B2Performing a multiply-multiply-accumulate instructionINTEL CORP·Filed 2013·Granted Mar 25, 2014·45 cites·20 claims
- 0296US9170955B2Providing extended cache replacement state informationINTEL CORP·Filed 2012·Granted Oct 27, 2015·59 cites·23 claims
- 0396US8669990B2Sharing resources between a CPU and GPUSPRANGLE ERIC·Filed 2009·Granted Mar 11, 2014·61 cites·29 claims
- 0494US8615647B2Migrating execution of thread between cores of different instruction set architecture in multi-core processor and transitioning each core to respective on / off power stateHUM HERBERT·Filed 2008·Granted Dec 24, 2013·34 cites·20 claims
- 0593US9829965B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Nov 28, 2017·11 cites·18 claims
- 0692US8930722B2Distribution of tasks among asymmetric processing elementsSPRANGLE ERIC·Filed 2009·Granted Jan 6, 2015·16 cites·21 claims
- 0785US9753530B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Sep 5, 2017·3 cites·6 claims
- 0884US8533436B2Adaptively handling remote atomic execution based upon contention predictionFRYMAN JOSHUA B·Filed 2009·Granted Sep 10, 2013·17 cites·20 claims
- 0982US11054890B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jul 6, 2021·3 cites·18 claims
- 1082US9760162B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Sep 12, 2017·3 cites·8 claims
- 1180US6925550B2Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detectionINTEL CORP·Filed 2002·Granted Aug 2, 2005·30 cites·23 claims
- 1279US9874926B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Jan 23, 2018·2 cites·12 claims
- 1378US9870046B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2013·Granted Jan 16, 2018·2 cites·12 claims
- 1474US11366511B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2020·Granted Jun 21, 2022·0 cites·29 claims
- 1573US9910483B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2014·Granted Mar 6, 2018·1 cites·4 claims
- 1672US9939882B2Systems and methods for migrating processes among asymmetrical processing coresINTEL CORP·Filed 2013·Granted Apr 10, 2018·1 cites·6 claims
- 1766US9110655B2Performing a multiply-multiply-accumulate instructionINTEL CORP·Filed 2014·Granted Aug 18, 2015·1 cites·20 claims
- 1863US10437320B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·15 claims
- 1963US10409360B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Sep 10, 2019·0 cites·9 claims
- 2063US10386915B2Distribution of tasks among asymmetric processing elementsINTEL CORP·Filed 2016·Granted Aug 20, 2019·0 cites·12 claims
- 2160US9792115B2Super multiply add (super MADD) instructions with three scalar termsCORBAL JESUS·Filed 2011·Granted Oct 17, 2017·1 cites·21 claims
- 2256US8933946B2Mechanism for effectively handling texture samplingSPRANGLE ERIC·Filed 2007·Granted Jan 13, 2015·0 cites·23 claims
- 2348US10181171B2Sharing resources between a CPU and GPUINTEL CORP·Filed 2013·Granted Jan 15, 2019·0 cites·19 claims
- 2446US2004199731A1Method and apparatus to control memory accessesFiled 2004·Application pending·0 cites
- 2544US8478969B2Performing a multiply-multiply-accumulate instructionSPRANGLE ERIC S·Filed 2010·Granted Jul 2, 2013·0 cites·20 claims
- 2644US2005071566A1Mechanism to increase data compression in a cacheFiled 2003·Application pending·0 cites
- 2743US2004193846A1Method and apparatus for utilizing multiple opportunity ports in a processor pipelineFiled 2003·Application pending·0 cites
- 2842US2004078558A1Method and apparatus to process instructions in a processorFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →