Method and apparatus to control memory accesses

Abstract

A method and apparatus for accessing memory comprising monitoring memory accesses from a hardware prefetcher; determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core; and switching memory accesses from a first mode to a second mode if a percentage of the memory access generated by the hardware prefetcher are used by the out-of-order core.

1 . An apparatus for accessing memory comprising: 
 a page open predictor to predict open memory pages;    a front side bus scheduler to switch memory access modes from a first mode to a second mode, said front side bus scheduler coupled to the page open predictor; and    a front side bus access queue, coupled to the front side bus scheduler, to contain memory accesses.    
     
     
         2 . The apparatus of  claim 1  further comprising a processor coupled to the front side bus access queue, wherein the processor comprises an out-of-order core and a hardware prefetcher.  
     
     
         3 . The apparatus of  claim 2  further comprising a memory controller coupled to the front side bus access queue.  
     
     
         4 . The apparatus of  claim 1  wherein the page open predictor predicts memory accesses that are predicted to occur from a page in memory.  
     
     
         5 . The apparatus of  claim 1  wherein the front side bus scheduler determines whether an application being processed is latency tolerant or latency intolerant.  
     
     
         6 . The apparatus of  claim 1  wherein the first mode comprises the front side bus scheduler scheduling memory accesses to minimize memory access latency, and the second mode comprises the front side bus scheduler scheduling memory accesses to maximize memory bus bandwidth.  
     
     
         7 . The apparatus of  claim 6  wherein the minimize memory access latency mode comprises the front side bus scheduler to first schedule memory accesses associated with earlier instructions.  
     
     
         8 . The apparatus of  claim 6  wherein maximize memory bus bandwidth mode comprises the front side bus scheduler to schedule memory accesses that are predicted to access data from an open memory page.  
     
     
         9 . The apparatus of  claim 1  wherein the front side bus scheduler searches a predetermined number of entries in the front side bus access queue to find entries that are predicted to access data from an open memory page, prior to scheduling a first entry in the front side bus access queue.  
     
     
         10 . The apparatus of  claim 5  wherein the front side bus scheduler automatically switches from the first mode to the second mode and vice versa.  
     
     
         11 . The apparatus of  claim 10  wherein the front side bus scheduler switches from the minimize memory access latency mode to the maximize memory bus bandwidth mode if for more than X percentage of accesses generated by a hardware prefetcher, more than Y percentage of accesses generated by the hardware prefetcher are also requested by an out-of-order core, based on any one of time and last n accesses and a weighted combination of time and last n accesses.  
     
     
         12 . A method comprising: 
 monitoring memory accesses generated by a hardware prefetcher;    determining whether the memory accesses from the hardware prefetcher are used by an out-of-order core; and    switching memory accesses from a first mode to a second mode if a percentage of the memory accesses generated by the hardware prefetcher are used by the out-of-order core.    
     
     
         13 . The method of  claim 12  wherein the percentage of the memory accesses generated by the hardware prefetcher that is used by the out-of-order core is at least 50 percent in a unit time.  
     
     
         14 - 19 . (Cancelled)  
     
     
         20 . A computer system comprising: 
 a bus;    a processor coupled to the bus;    a front side bus controller coupled to the bus, said front side bus controller comprising a page open predictor, and a front side bus scheduler, said front side bus scheduler to switch memory access modes from a first mode to a second mode, said front side bus scheduler coupled to the page open predictor; and    a front side bus access queue, coupled to the front side bus scheduler, to contain memory accesses.    
     
     
         21 . The computer system of  claim 20  wherein the processor comprises an out-of-order core and a hardware prefetcher.  
     
     
         22 . The computer system of  claim 20  wherein the page open predictor predicts memory accesses that are likely to occur from a page in memory.  
     
     
         23 . The computer system of  claim 20  wherein the front side bus scheduler switches memory access modes from a first mode to a second mode.  
     
     
         24 . The computer system of  claim 23  wherein the first mode comprises memory accesses to minimize memory access latency, and the second mode comprises memory accesses to maximize memory bus bandwidth.  
     
     
         25 . The computer system of  claim 24  wherein the minimizing memory access latency mode comprises the front side bus scheduler to first schedule memory accesses generated by earlier instructions.  
     
     
         26 . The computer system of  claim 24  wherein maximizing memory bus bandwidth mode comprises the front side bus scheduler to schedule memory accesses that are predicted to access data from an open memory page.  
     
     
         27 . The computer system of  claim 24  wherein in the maximizing bus bandwidth mode the front side bus scheduler searches a predetermined number of entries in the front side bus access queue to find entries that are predicted to access data from an open memory page, prior to scheduling a first entry in the front side bus access queue.  
     
     
         28 . (Cancelled)  
     
     
         29 . The computer system of  claim 26  wherein the front side bus scheduler switches from the minimize memory access latency mode to the maximize memory bus bandwidth mode dynamically.  
     
     
         30 . (Cancelled)