Inventor · disambiguated record
Eswararao Potladhurthi
Also filed as: POTLADHURTHI ESWARARAO
8 granted patents·1 pending application·30 citations·filing 2009–2019
84Inventor score
Technology areasG11C
Top patents by PatentIndex Score
9 records- 0194US9496025B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2015·Granted Nov 15, 2016·20 cites·17 claims
- 0286US9847119B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2016·Granted Dec 19, 2017·5 cites·14 claims
- 0373US9984742B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2016·Granted May 29, 2018·2 cites·11 claims
- 0468US10522217B1Column-dependent positive voltage boost for memory cell supply voltageGLOBALFOUNDRIES INC·Filed 2018·Granted Dec 31, 2019·2 cites·20 claims
- 0567US10217510B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2017·Granted Feb 26, 2019·1 cites·7 claims
- 0655US10783958B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2019·Granted Sep 22, 2020·0 cites·11 claims
- 0754US10783956B2Tunable negative bitline write assist and boost attenuation circuitIBM·Filed 2019·Granted Sep 22, 2020·0 cites·18 claims
- 0851US10319431B2Tunable negative bit line write assist and boost attenuation circuitIBM·Filed 2017·Granted Jun 11, 2019·0 cites·9 claims
- 0937US2011133809A1Semiconductor device and method for cancelling offset voltage of sense amplifierELPIDA MEMORY INC·Filed 2009·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Eswararao Potladhurthi files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →