Inventor · disambiguated record
Federico Pio
Also filed as: PIO FEDERICO
83 granted patents·4 pending applications·1,096 citations·filing 1992–2025
99Inventor score
Files withST MICROELECTRONICS SRL40MICRON TECHNOLOGY INC24PIO FEDERICO9SGS THOMSON MICROELECTRONICS9INTEL CORP2
Top patents by PatentIndex Score
87 records- 0199US9799381B1Double-polarity memory readINTEL CORP·Filed 2016·Granted Oct 24, 2017·81 cites·21 claims
- 0298US10431301B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2017·Granted Oct 1, 2019·39 cites·13 claims
- 0398US8841649B2Three dimensional memory array architecturePIO FEDERICO·Filed 2012·Granted Sep 23, 2014·65 cites·29 claims
- 0498US8729523B2Three dimensional memory array architecturePIO FEDERICO·Filed 2012·Granted May 20, 2014·68 cites·32 claims
- 0597US9252362B2Method for making three dimensional memory array architecture using phase change and ovonic switching materialsMICRON TECHNOLOGY INC·Filed 2014·Granted Feb 2, 2016·28 cites·20 claims
- 0695US12131916B2Semiconductor packages with patterns of die-specific informationMICRON TECHNOLOGY INC·Filed 2021·Granted Oct 29, 2024·2 cites·18 claims
- 0794US10600480B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2019·Granted Mar 24, 2020·8 cites·20 claims
- 0894US7345905B2Memory device with time-shifting based emulation of reference cellsST MICROELECTRONICS SRL·Filed 2006·Granted Mar 18, 2008·41 cites·27 claims
- 0993US9444046B2Three dimensional memory array architectureMICRON TECHNOLOGY INC·Filed 2014·Granted Sep 13, 2016·13 cites·19 claims
- 1092US9595667B2Three dimensional memory array architectureMICRON TECHNOLOGY INC·Filed 2016·Granted Mar 14, 2017·6 cites·16 claims
- 1192US5792670AMethod of manufacturing double polysilicon EEPROM cell and access transistorST MICROELECTRONICS SRL·Filed 1995·Granted Aug 11, 1998·76 cites·10 claims
- 1291US12277969B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2024·Granted Apr 15, 2025·0 cites·20 claims
- 1391US11031258B2Semiconductor packages with patterns of die-specific informationMICRON TECHNOLOGY INC·Filed 2019·Granted Jun 8, 2021·4 cites·17 claims
- 1489US6643184B2Method of erasing a flash memoryST MICROELECTRONICS SRL·Filed 2002·Granted Nov 4, 2003·49 cites·22 claims
- 1588US8248851B1System, apparatus, and reading method for NAND memoriesPIO FEDERICO·Filed 2009·Granted Aug 21, 2012·20 cites·18 claims
- 1686US7630263B2Exploiting a statistical distribution of the values of an electrical characteristic in a population of auxiliary memory cells for obtaining reference cellsPIO FEDERICO·Filed 2005·Granted Dec 8, 2009·17 cites·4 claims
- 1784US10102891B2Double-polarity memory readINTEL CORP·Filed 2017·Granted Oct 16, 2018·5 cites·20 claims
- 1883US8093090B1Integrated circuit edge and method to fabricate the samePIO FEDERICO·Filed 2009·Granted Jan 10, 2012·7 cites·18 claims
- 1981US12009028B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2022·Granted Jun 11, 2024·0 cites·20 claims
- 2081US8737138B2Memory instruction including parameter to affect operating condition of memoryPIO FEDERICO·Filed 2010·Granted May 27, 2014·5 cites·29 claims
- 2181US5936298AMethod for realizing magnetic circuits in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Aug 10, 1999·67 cites·21 claims
- 2280US2025266088A1Systems and techniques for accessing multiple memory cells concurrentlyMICRON TECHNOLOGY INC·Filed 2025·Application pending·0 cites
- 2378US6128219ANonvolatile memory test structure and nonvolatile memory reliability test methodST MICROELECTRONICS SRL·Filed 1999·Granted Oct 3, 2000·47 cites·29 claims
- 2477US12249370B2Systems and techniques for accessing multiple memory cells concurrentlyMICRON TECHNOLOGY INC·Filed 2023·Granted Mar 11, 2025·0 cites·22 claims
- 2576US6668303B2Method for refreshing stored data in an electrically erasable and programmable non-volatile memoryST MICROELECTRONICS SRL·Filed 2002·Granted Dec 23, 2003·24 cites·22 claims
- 2676US6548355B2EEPROM memory cell and corresponding manufacturing methodST MICROELECTRONICS SRL·Filed 2001·Granted Apr 15, 2003·18 cites·13 claims
- 2776US5793673ADouble polysilicon EEPROM cell and corresponding manufacturing process and programming methodST MICROELECTRONICS SRL·Filed 1997·Granted Aug 11, 1998·29 cites·22 claims
- 2875US6865114B2Word line selector for a semiconductor memoryST MICROELECTRONICS SRL·Filed 2003·Granted Mar 8, 2005·22 cites·28 claims
- 2974US8728856B2Method of manufacturing upwardly tapering heaters for phase change memoriesMICRON TECHNOLOGY INC·Filed 2013·Granted May 20, 2014·2 cites·18 claims
- 3074US8361833B2Upwardly tapering heaters for phase change memoriesMICRON TECHNOLOGY INC·Filed 2010·Granted Jan 29, 2013·2 cites·22 claims
- 3174US6259132B1Array of electrically programmable non-volatile semiconductor memory cells comprising ROM memory cellsST MICROELECTRONICS SRL·Filed 1998·Granted Jul 10, 2001·31 cites·43 claims
- 3273US11705194B2Systems and techniques for accessing multiple memory cells concurrentlyMICRON TECHNOLOGY INC·Filed 2022·Granted Jul 18, 2023·0 cites·20 claims
- 3373US10114746B2Nonvolatile storage using low latency and high latency memoryPIO FEDERICO·Filed 2010·Granted Oct 30, 2018·3 cites·18 claims
- 3472US9437254B2Method of dynamically selecting memory cell capacityMICRON TECHNOLOGY INC·Filed 2015·Granted Sep 6, 2016·2 cites·19 claims
- 3571US6115313AMethod for saving data in the event of unwanted interruptions in the programming cycle of a nonvolatile memory, and a nonvolatile memoryST MICROELECTRONICS SRL·Filed 1999·Granted Sep 5, 2000·28 cites·30 claims
- 3670US11282574B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2020·Granted Mar 22, 2022·0 cites·20 claims
- 3770US7529136B2Method for compacting the erased threshold voltage distribution of flash memory devices during writing operationsMICHELONI RINO·Filed 2007·Granted May 5, 2009·7 cites·11 claims
- 3869US9076524B2Method of accessing a memory deviceMICRON TECHNOLOGY INC·Filed 2014·Granted Jul 7, 2015·1 cites·19 claims
- 3969US6815328B2Method of manufacturing an integrated semiconductor device having a plurality of connection levelsST MICROELECTRONICS SRL·Filed 2001·Granted Nov 9, 2004·16 cites·26 claims
- 4069US2023121141A1Semiconductor packages with indications of die-specific informationMICRON TECHNOLOGY INC·Filed 2022·Application pending·0 cites
- 4168US10896727B2Auto-referenced memory cell read techniquesMICRON TECHNOLOGY INC·Filed 2020·Granted Jan 19, 2021·0 cites·20 claims
- 4268US6278159B1Process for the manufacture of integrated devices with gate oxide protection from manufacturing process damage, and protection structure thereforST MICROELECTRONICS SRL·Filed 1999·Granted Aug 21, 2001·24 cites·15 claims
- 4366US8759969B1Integrated circuit dice with edge finishingPIO FEDERICO·Filed 2012·Granted Jun 24, 2014·1 cites·20 claims
- 4463US6803630B2Method of adjusting program voltage in non-volatile memories, and process for fabricating a non-volatile memory deviceST MICROELECTRONICS SRL·Filed 2003·Granted Oct 12, 2004·11 cites·6 claims
- 4563US6268633B1Electronic structure comprising high and low voltage transistors, and a corresponding fabrication methodST MICROELECTRONICS SRL·Filed 1998·Granted Jul 31, 2001·18 cites·17 claims
- 4663US5894146AEEPROM memory cells matrix with double polysilicon level and relating manufacturing processSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Apr 13, 1999·22 cites·18 claims
- 4762US11532490B2Semiconductor packages with indications of die-specific informationMICRON TECHNOLOGY INC·Filed 2019·Granted Dec 20, 2022·0 cites·17 claims
- 4862US6309972B1Method of enhancing protection of dielectrics from plasma induced damages and equipmentST MICROELECTRONICS SRL·Filed 1999·Granted Oct 30, 2001·26 cites·14 claims
- 4961US6127224AProcess for forming a non-volatile memory cell with silicided contactsST MICROELECTRONICS SRL·Filed 1998·Granted Oct 3, 2000·15 cites·14 claims
- 5060US10452541B2Nonvolatile storage using low latency and high latency memoryMICRON TECHNOLOGY INC·Filed 2018·Granted Oct 22, 2019·0 cites·20 claims
Showing the top 50 of 87 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →