Inventor · disambiguated record
Frank Koschinsky
Also filed as: KOSCHINSKY FRANK
16 granted patents·6 pending applications·130 citations·filing 2002–2016
91Inventor score
Top patents by PatentIndex Score
22 records- 0194US9177858B1Methods for fabricating integrated circuits including barrier layers for interconnect structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·32 cites·20 claims
- 0284US6613660B2Metallization process sequence for a barrier metal layerADVANCED MICRO DEVICES INC·Filed 2002·Granted Sep 2, 2003·44 cites·28 claims
- 0382US6964874B2Void formation monitoring in a damascene processADVANCED MICRO DEVICES INC·Filed 2002·Granted Nov 15, 2005·30 cites·43 claims
- 0481US8053354B2Reduced wafer warpage in semiconductors by stress engineering in the metallization systemGLOBALFOUNDRIES INC·Filed 2009·Granted Nov 8, 2011·7 cites·16 claims
- 0570US8585877B2Multi-step deposition controlJAEGER ROLAND·Filed 2012·Granted Nov 19, 2013·3 cites·18 claims
- 0670US8163571B2Multi-step deposition controlJAEGER ROLAND·Filed 2008·Granted Apr 24, 2012·4 cites·8 claims
- 0769US7820536B2Method for removing a passivation layer prior to depositing a barrier layer in a copper metallization layerADVANCED MICRO DEVICES INC·Filed 2006·Granted Oct 26, 2010·3 cites·19 claims
- 0864US9147618B2Method for detecting defects in a diffusion barrier layerGLOBALFOUNDRIES INC·Filed 2013·Granted Sep 29, 2015·2 cites·20 claims
- 0964US8323989B2Test system and method of reducing damage in seed layers in metallization systems of semiconductor devicesFEUSTEL FRANK·Filed 2010·Granted Dec 4, 2012·2 cites·15 claims
- 1058US8039400B2Reducing contamination of semiconductor substrates during BEOL processing by performing a deposition/etch cycle during barrier depositionGLOBALFOUNDRIES INC·Filed 2009·Granted Oct 18, 2011·1 cites·25 claims
- 1156US9177826B2Methods of forming metal nitride materialsHINTZE BERND·Filed 2012·Granted Nov 3, 2015·1 cites·28 claims
- 1243US8058081B2Method of testing an integrity of a material layer in a semiconductor structureMEYER MORITZ ANDREAS·Filed 2007·Granted Nov 15, 2011·0 cites·18 claims
- 1342US6716650B2Interface void monitoring in a damascene processADVANCED MICRO DEVICES INC·Filed 2002·Granted Apr 6, 2004·1 cites·22 claims
- 1442US2007096221A1Semiconductor device comprising copper-based contact plug and a method of forming the sameFROHBERG KAI·Filed 2006·Application pending·0 cites
- 1541US10090195B2Method including a formation of a diffusion barrier and semiconductor structure including a diffusion barrierGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 2, 2018·0 cites·20 claims
- 1641US7063091B2Method for cleaning the surface of a substrateADVANCED MICRO DEVICES INC·Filed 2005·Granted Jun 20, 2006·0 cites·34 claims
- 1741US2007077761A1Technique for forming a copper-based metallization layer including a conductive capping layerLEHR MATTHIAS·Filed 2006·Application pending·0 cites
- 1840US2014273436A1Methods of forming barrier layers for conductive copper structuresGLOBALFOUNDRIES INC·Filed 2013·Application pending·0 cites
- 1940US2006267207A1Method of forming electrically conductive lines in an integrated circuitFEUSTEL FRANK·Filed 2006·Application pending·0 cites
- 2039US9171754B2Method including an etching of a portion of an interlayer dielectric in a semiconductor structure, a degas process and a preclean processGLOBALFOUNDRIES INC·Filed 2013·Granted Oct 27, 2015·0 cites·28 claims
- 2139US2006267201A1Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layerHUEBLER PETER·Filed 2005·Application pending·0 cites
- 2232US2014024213A1Processes for forming integrated circuits with post-patterning treamentHINTZE BERND·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →