Inventor · disambiguated record
Frederic Lazzarino
Also filed as: LAZZARINO FREDERIC
13 granted patents·1 pending application·3 citations·filing 2014–2022
81Inventor score
Top patents by PatentIndex Score
14 records- 0173US10770295B2Patterning methodIMEC VZW·Filed 2019·Granted Sep 8, 2020·2 cites·15 claims
- 0264US10593549B2Method for defining patterns for conductive paths in a dielectric layerIMEC VZW·Filed 2018·Granted Mar 17, 2020·1 cites·9 claims
- 0363US11495490B2Semiconductor device manufacturing methodTOKYO ELECTRON LTD·Filed 2020·Granted Nov 8, 2022·0 cites·5 claims
- 0455US10910259B2Semiconductor device manufacturing methodTOKYO ELECTRON LTD·Filed 2018·Granted Feb 2, 2021·0 cites·8 claims
- 0549US12261045B2Patterning methodIMEC VZW·Filed 2022·Granted Mar 25, 2025·0 cites·15 claims
- 0649US12154794B2Method of etching an indium gallium zinc oxide (IGZO) structureIMEC VZW·Filed 2021·Granted Nov 26, 2024·0 cites·19 claims
- 0745US11127627B2Method for forming an interconnection structureIMEC VZW·Filed 2019·Granted Sep 21, 2021·0 cites·10 claims
- 0844US11710637B2Patterning methodIMEC VZW·Filed 2021·Granted Jul 25, 2023·0 cites·20 claims
- 0944US11476155B2Patterning methodIMEC VZW·Filed 2021·Granted Oct 18, 2022·0 cites·20 claims
- 1044US10707198B2Patterning a target layerIMEC VZW·Filed 2018·Granted Jul 7, 2020·0 cites·16 claims
- 1144US9437488B2Metallization method for semiconductor structuresIMEC VZW·Filed 2015·Granted Sep 6, 2016·0 cites·15 claims
- 1242US10651076B2Method for defining patterns for conductive paths in dielectric layerIMEC VZW·Filed 2018·Granted May 12, 2020·0 cites·20 claims
- 1341US2014291289A1Method for etching porous organosilica low-k materialsTOKYO ELECTRON LTD·Filed 2014·Application pending·0 cites
- 1437US10818504B2Method for producing a pattern of features by lithography and etchingIMEC VZW·Filed 2018·Granted Oct 27, 2020·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →