Inventor · disambiguated record
Fu-Chang Hsu
Also filed as: HSU FU-CHANG
131 granted patents·43 pending applications·4,139 citations·filing 1996–2024
99Inventor score
Files withAPLUS FLASH TECHNOLOGY INC65HSU FU CHANG32NEO SEMICONDUCTOR INC32LEE PETER WUNG23APLUS INTEGRATED CIRCUITS INC15
Top patents by PatentIndex Score
174 records- 0198US11049579B2Methods and apparatus for NAND flash memoryHSU FU CHANG·Filed 2020·Granted Jun 29, 2021·9 cites·19 claims
- 0298US6862223B1Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 1, 2005·130 cites·28 claims
- 0398US6714457B1Parallel channel programming scheme for MLC flash memoryAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Mar 30, 2004·164 cites·36 claims
- 0498US5768193ABit-refreshable method and circuit for refreshing a nonvolatile flash memoryAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jun 16, 1998·207 cites·19 claims
- 0597US8773903B2High speed high density nand-based 2T-NOR flash memory designLEE PETER WUNG·Filed 2012·Granted Jul 8, 2014·33 cites·33 claims
- 0697US8120959B2NAND string based NAND/NOR flash memory cell, array, and memory device having parallel bit lines and source lines, having a programmable select gating transistor, and circuits and methods for operating sameLEE PETER WUNG·Filed 2009·Granted Feb 21, 2012·73 cites·56 claims
- 0797US7102929B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 5, 2006·51 cites·5 claims
- 0896US6620682B1Set of three level concurrent word line bias conditions for a nor type flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Sep 16, 2003·110 cites·8 claims
- 0996US5822252AFlash memory wordline decoder with overerase repairAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Oct 13, 1998·181 cites·28 claims
- 1096US5748538AOR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted May 5, 1998·182 cites·10 claims
- 1195US7110302B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Sep 19, 2006·25 cites·52 claims
- 1295US7075826B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Jul 11, 2006·28 cites·8 claims
- 1395US6850438B2Combination nonvolatile memory using unified technology with byte, page and block write and simultaneous read and write operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Feb 1, 2005·75 cites·23 claims
- 1495US6556481B13-step write operation nonvolatile semiconductor one-transistor, nor-type flash EEPROM memory cellAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Apr 29, 2003·114 cites·22 claims
- 1595US5978283ACharge pump circuitsAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Nov 2, 1999·147 cites·18 claims
- 1694US6757196B1Two transistor flash memory cell for use in EEPROM arrays with a programmable logic deviceAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Jun 29, 2004·83 cites·39 claims
- 1794US5835420ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Nov 10, 1998·104 cites·34 claims
- 1894US5748545AMemory device with on-chip manufacturing and memory cell defect detection capabilityAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted May 5, 1998·116 cites·40 claims
- 1993US10008265B2Method and apparatus for providing three-dimensional integrated nonvolatile memory (NVM) and dynamic random access memory (DRAM) memory deviceNEO SEMICONDUCTOR INC·Filed 2015·Granted Jun 26, 2018·14 cites·22 claims
- 2093US7830713B2Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash arrayAPLUS FLASH TECHNOLOGY INC·Filed 2008·Granted Nov 9, 2010·25 cites·48 claims
- 2193US7324384B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Jan 29, 2008·18 cites·20 claims
- 2293US6498752B1Three step write process used for a nonvolatile NOR type EEPROM memoryAPLUS FLASH TECHNOLOGY INC·Filed 2001·Granted Dec 24, 2002·83 cites·39 claims
- 2393US6381670B1Flash memory array having maximum and minimum threshold voltage detection for eliminating over-erasure problem and enhancing write operationAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Apr 30, 2002·147 cites·43 claims
- 2492US9761310B2Method and apparatus for storing information using a memory able to perform both NVM and DRAM functionsNEO SEMICONDUCTOR INC·Filed 2015·Granted Sep 12, 2017·11 cites·17 claims
- 2592US6788612B2Flash memory array structure suitable for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Sep 7, 2004·50 cites·9 claims
- 2692US6023188APositive/negative high voltage charge pump systemAPLUS FLASH TECHNOLOGY INC·Filed 1999·Granted Feb 8, 2000·101 cites·20 claims
- 2792US6009022ANode-precise voltage regulation for a MOS memory systemAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Dec 28, 1999·83 cites·20 claims
- 2891US8335108B2Bit line gate transistor structure for a multilevel, dual-sided nonvolatile memory cell NAND flash arrayLEE PETER WUNG·Filed 2008·Granted Dec 18, 2012·19 cites·28 claims
- 2991US8289775B2Apparatus and method for inhibiting excess leakage current in unselected nonvolatile memory cells in an arrayLEE PETER WUNG·Filed 2009·Granted Oct 16, 2012·24 cites·77 claims
- 3091US7636252B2Nonvolatile memory with a unified cell structureLEE PETER W·Filed 2006·Granted Dec 22, 2009·17 cites·20 claims
- 3191US7289366B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Oct 30, 2007·19 cites·40 claims
- 3291US7120064B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2005·Granted Oct 10, 2006·15 cites·20 claims
- 3391US5930826AFlash memory protection attribute status bits held in a flash memory arrayAPLUS INTEGRATED CIRCUITS INC·Filed 1997·Granted Jul 27, 1999·94 cites·12 claims
- 3491US5777923AFlash memory read/write controllerAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jul 7, 1998·79 cites·22 claims
- 3590US8455923B2Embedded NOR flash memory process with NAND cell and true logic compatible low voltage deviceLEE PETER WUNG·Filed 2011·Granted Jun 4, 2013·10 cites·66 claims
- 3690US8072811B2NAND based NMOS NOR flash memory cell, a NAND based NMOS NOR flash memory array, and a method of forming a NAND based NMOS NOR flash memory arrayLEE PETER WUNG·Filed 2009·Granted Dec 6, 2011·18 cites·92 claims
- 3790US7283401B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2006·Granted Oct 16, 2007·17 cites·10 claims
- 3890US6660585B1Stacked gate flash memory cell with reduced disturb conditionsAPLUS FLASH TECHNOLOGY INC·Filed 2000·Granted Dec 9, 2003·48 cites·1 claims
- 3990US6031765AReversed split-gate cell arrayAPLUS FLASH TECHNOLOGY INC·Filed 1999·Granted Feb 29, 2000·77 cites·16 claims
- 4089US11056190B2Methods and apparatus for NAND flash memoryNEO SEMICONDUCTOR INC·Filed 2019·Granted Jul 6, 2021·8 cites·4 claims
- 4189US8331150B2Integrated SRAM and FLOTOX EEPROM memory deviceHSU FU-CHANG·Filed 2009·Granted Dec 11, 2012·22 cites·90 claims
- 4289US8149622B2Memory system having NAND-based NOR and NAND flashes and SRAM integrated in one chip for hybrid data, code and cache storageLEE PETER WUNG·Filed 2010·Granted Apr 3, 2012·13 cites·73 claims
- 4389US6240027B1Approach to provide high external voltage for flash memory eraseAPLUS FLASH TECHNOLOGY INC·Filed 2000·Granted May 29, 2001·49 cites·10 claims
- 4489US5978277ABias condition and X-decoder circuit of flash memory arrayAPLUS FLASH TECHNOLOGY INC·Filed 1998·Granted Nov 2, 1999·72 cites·37 claims
- 4588US9793001B2CMOS anti-fuse cellNEO SEMICONDUCTOR INC·Filed 2016·Granted Oct 17, 2017·4 cites·20 claims
- 4688US6628563B1Flash memory array for multiple simultaneous operationsAPLUS FLASH TECHNOLOGY INC·Filed 2002·Granted Sep 30, 2003·48 cites·35 claims
- 4788US5774396AFlash memory with row redundancyAPLUS INTEGRATED CIRCUITS INC·Filed 1996·Granted Jun 30, 1998·71 cites·30 claims
- 4887US7064978B2Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutAPLUS FLASH TECHNOLOGY INC·Filed 2003·Granted Jun 20, 2006·33 cites·10 claims
- 4987US5917757AFlash memory with high speed erasing structure using thin oxide semiconductor devicesAPLUS FLASH TECHNOLOGY INC·Filed 1997·Granted Jun 29, 1999·67 cites·40 claims
- 5086US12217808B2Methods and apparatus for NAND flash memoryNEO SEMICONDUCTOR INC·Filed 2022·Granted Feb 4, 2025·1 cites·11 claims
Showing the top 50 of 174 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →