Inventor · disambiguated record
G. Michael Uhler
Also filed as: UHLER G M · UHLER G MICHAEL
28 granted patents·1 pending application·1,544 citations·filing 1987–2009
98Inventor score
Top patents by PatentIndex Score
29 records- 0197US5481689AConversion of internal processor register commands to I/O space addressesDIGITAL EQUIPMENT CORP·Filed 1993·Granted Jan 2, 1996·95 cites·11 claims
- 0294US7853777B2Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructionsMIPS TECH INC·Filed 2005·Granted Dec 14, 2010·43 cites·38 claims
- 0393US7185183B1Atomic update of CPO stateMIPS TECH INC·Filed 2001·Granted Feb 27, 2007·96 cites·21 claims
- 0491US7181600B1Read-only access to CPO registersMIPS TECH INC·Filed 2001·Granted Feb 20, 2007·73 cites·21 claims
- 0586US7724261B2Processor having a compare extension of an instruction set architectureMIPS TECH INC·Filed 2007·Granted May 25, 2010·13 cites·12 claims
- 0686US5802272AMethod and apparatus for tracing unpredictable execution flows in a trace buffer of a high-speed computer systemDIGITAL EQUIPMENT CORP·Filed 1994·Granted Sep 1, 1998·116 cites·25 claims
- 0784US6651156B1Mechanism for extending properties of virtual memory pages by a TLBMIPS TECH INC·Filed 2001·Granted Nov 18, 2003·40 cites·19 claims
- 0884US5764885AApparatus and method for tracing data flows in high-speed computer systemsDIGITAL EQUIPMENT CORP·Filed 1994·Granted Jun 9, 1998·108 cites·23 claims
- 0984US5119483AApplication of state silos for recovery from memory management exceptionsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Jun 2, 1992·85 cites·20 claims
- 1084US5058006AMethod and apparatus for filtering invalidate requestsDIGITAL EQUIPMENT CORP·Filed 1988·Granted Oct 15, 1991·86 cites·6 claims
- 1181US6493776B1Scalable on-chip system busMIPS TECH INC·Filed 1999·Granted Dec 10, 2002·95 cites·28 claims
- 1279US6240508B1Decode and execution synchronized pipeline processing using decode generated memory read queue with stop entry to allow execution generated memory readCOMPAQ COMPUTER CORP·Filed 1995·Granted May 29, 2001·91 cites·21 claims
- 1378US7242414B1Processor having a compare extension of an instruction set architectureMIPS TECH INC·Filed 1999·Granted Jul 10, 2007·71 cites·26 claims
- 1478US6681283B1Coherent data apparatus for an on-chip split transaction system busMIPS TECH INC·Filed 1999·Granted Jan 20, 2004·77 cites·39 claims
- 1578US6490642B1Locked read/write on separate address/data bus using write barrierMIPS TECH INC·Filed 1999·Granted Dec 3, 2002·80 cites·25 claims
- 1675US5542058APipelined computer with operand context queue to simplify context-dependent execution flowDIGITAL EQUIPMENT CORP·Filed 1994·Granted Jul 30, 1996·66 cites·20 claims
- 1774US5450349AComputer system performance evaluation system and methodDIGITAL EQUIPMENT CORP·Filed 1992·Granted Sep 12, 1995·66 cites·8 claims
- 1872US8171262B2Method and apparatus for clearing hazards using jump instructionsJEPPESEN NIELS GRAM·Filed 2005·Granted May 1, 2012·9 cites·51 claims
- 1968US7487339B2Method and apparatus for binding shadow registers to vectored interruptsMIPS TECH INC·Filed 2001·Granted Feb 3, 2009·9 cites·35 claims
- 2068US5579504AMulti-processor computer system having shared memory, private cache memories, and invalidate queues having valid bits and flush bits for serializing transactionsDIGITAL EQUIPMENT CORP·Filed 1995·Granted Nov 26, 1996·58 cites·9 claims
- 2167US7925864B2Method and apparatus for binding shadow registers to vectored interruptsMIPS TECH INC·Filed 2009·Granted Apr 12, 2011·2 cites·17 claims
- 2265US6714197B1Processor having an arithmetic extension of an instruction set architectureMIPS TECH INC·Filed 1999·Granted Mar 30, 2004·45 cites·61 claims
- 2364US7065675B1System and method for speeding up EJTAG block data transfersMIPS TECH INC·Filed 2001·Granted Jun 20, 2006·11 cites·34 claims
- 2463US4851991ACentral processor unit for digital data processing system including write buffer management mechanismDIGITAL EQUIPMENT CORP·Filed 1987·Granted Jul 25, 1989·33 cites·19 claims
- 2561US6604159B1Data release to reduce latency in on-chip system busMIPS TECH INC·Filed 1999·Granted Aug 5, 2003·36 cites·28 claims
- 2657US7552261B2Configurable prioritization of core generated interruptsMIPS TECH INC·Filed 2001·Granted Jun 23, 2009·5 cites·34 claims
- 2757US6732259B1Processor having a conditional branch extension of an instruction set architectureMIPS TECH INC·Filed 1999·Granted May 4, 2004·32 cites·78 claims
- 2850US7000095B2Method and apparatus for clearing hazards using jump instructionsMIPS TECH INC·Filed 2002·Granted Feb 14, 2006·3 cites·20 claims
- 2945US2005182903A1Apparatus and method for preventing duplicate matching entries in a translation lookaside bufferMIPS TECH INC·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →