Inventor · disambiguated record
Gautham Chinya
Also filed as: CHINYA GAUTHAM · CHINYA GAUTHAM N
64 granted patents·16 pending applications·344 citations·filing 2004–2025
98Inventor score
Top patents by PatentIndex Score
80 records- 0197US7882339B2Primitives to enhance thread-level speculationINTEL CORP·Filed 2005·Granted Feb 1, 2011·56 cites·11 claims
- 0291US8108863B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2005·Granted Jan 31, 2012·30 cites·24 claims
- 0390US12141683B2Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2021·Granted Nov 12, 2024·3 cites·20 claims
- 0489US7941791B2Programming environment for heterogeneous processor resource integrationWANG PERRY·Filed 2007·Granted May 10, 2011·31 cites·12 claims
- 0588US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 0687US8479217B2Apparatus, system, and method for persistent user-level threadCHINYA GAUTHAM·Filed 2011·Granted Jul 2, 2013·7 cites·19 claims
- 0787US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 0887US7768518B2Enabling multiple instruction stream/multiple data stream extensions on microprocessorsINTEL CORP·Filed 2006·Granted Aug 3, 2010·19 cites·15 claims
- 0986US8719547B2Providing hardware support for shared virtual memory between local and remote physical memoryCHINYA GAUTHAM N·Filed 2009·Granted May 6, 2014·20 cites·29 claims
- 1085US8762694B1Programmable event-driven yield mechanismZOU XIANG·Filed 2006·Granted Jun 24, 2014·24 cites·26 claims
- 1185US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 1285US2025365009A1Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2025·Application pending·0 cites
- 1381US11922178B2Methods and apparatus to load data within a machine learning acceleratorINTEL CORP·Filed 2021·Granted Mar 5, 2024·1 cites·20 claims
- 1481US10341669B2Temporally encoding a static spatial imageINTEL CORP·Filed 2016·Granted Jul 2, 2019·5 cites·24 claims
- 1581US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 1679US8516483B2Transparent support for operating system services for a sequestered sequencerCHINYA GAUTHAM·Filed 2005·Granted Aug 20, 2013·10 cites·26 claims
- 1778US12438553B2Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2023·Granted Oct 7, 2025·0 cites·20 claims
- 1878US9003164B2Providing hardware support for shared virtual memory between local and remote physical memoryINTEL CORP·Filed 2014·Granted Apr 7, 2015·4 cites·20 claims
- 1978US7810083B2Mechanism to emulate user-level multithreading on an OS-sequestered sequencerINTEL CORP·Filed 2004·Granted Oct 5, 2010·25 cites·37 claims
- 2075US12288153B2Schedule-aware tensor distribution moduleINTEL CORP·Filed 2024·Granted Apr 29, 2025·0 cites·20 claims
- 2175US12242861B2Methods and apparatus to load data within a machine learning acceleratorINTEL CORP·Filed 2024·Granted Mar 4, 2025·0 cites·17 claims
- 2274US8028295B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2005·Granted Sep 27, 2011·4 cites·21 claims
- 2374US2025036928A1Performance scaling for dataflow deep neural network hardware acceleratorsINTEL CORP·Filed 2024·Application pending·0 cites
- 2473US10867142B2Multiplication-free approximation for neural networks and sparse codingINTEL CORP·Filed 2016·Granted Dec 15, 2020·2 cites·6 claims
- 2573US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 2673US8171268B2Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectorsNEWBURN CHRIS J·Filed 2005·Granted May 1, 2012·7 cites·5 claims
- 2772US11714977B2Multiplication-free approximation for neural networks and sparse codingINTEL CORP·Filed 2021·Granted Aug 1, 2023·0 cites·6 claims
- 2869US8689215B2Structured exception handling for application-managed thread unitsHANKINS RICHARD A·Filed 2006·Granted Apr 1, 2014·5 cites·28 claims
- 2969US8332619B2Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2011·Granted Dec 11, 2012·2 cites·12 claims
- 3069US8079035B2Data structure and management techniques for local user-level thread dataHANKINS RICHARD A·Filed 2005·Granted Dec 13, 2011·5 cites·23 claims
- 3168US9112884B2Device-to-device communication for resource sharingINTEL CORP·Filed 2013·Granted Aug 18, 2015·2 cites·25 claims
- 3268US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 3367US11232273B2Multiplication-free approximation for neural networks and sparse codingINTEL CORP·Filed 2020·Granted Jan 25, 2022·0 cites·6 claims
- 3467US8214574B2Event handling for architectural events at high privilege levelsCHINYA GAUTHAM·Filed 2006·Granted Jul 3, 2012·4 cites·21 claims
- 3566US8914618B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceWANG HONG·Filed 2005·Granted Dec 16, 2014·3 cites·10 claims
- 3665US11804851B2Methods, systems, articles of manufacture, and apparatus to decode zero-value-compression data vectorsINTEL CORP·Filed 2020·Granted Oct 31, 2023·0 cites·21 claims
- 3765US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 3865US8074274B2User-level privilege managementWANG HONG·Filed 2006·Granted Dec 6, 2011·3 cites·23 claims
- 3964US10534613B2Supporting learned branch predictorsINTEL CORP·Filed 2017·Granted Jan 14, 2020·1 cites·20 claims
- 4064US10158582B2Device-to-device communication for resource sharingINTEL CORP·Filed 2015·Granted Dec 18, 2018·1 cites·30 claims
- 4164US9459874B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceINTEL CORP·Filed 2014·Granted Oct 4, 2016·1 cites·18 claims
- 4264US8839258B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2012·Granted Sep 16, 2014·1 cites·29 claims
- 4364US7631125B2Dynamically migrating channelsINTEL CORP·Filed 2005·Granted Dec 8, 2009·2 cites·27 claims
- 4463US9588771B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceINTEL CORP·Filed 2013·Granted Mar 7, 2017·1 cites·18 claims
- 4560US11048318B2Reducing microprocessor power with minimal performance impact by dynamically adapting runtime operating configurations using machine learningINTEL CORP·Filed 2019·Granted Jun 29, 2021·1 cites·18 claims
- 4660US9875102B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Jan 23, 2018·0 cites·20 claims
- 4759US9766891B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 4859US7991965B2Technique for using memory attributesINTEL CORP·Filed 2006·Granted Aug 2, 2011·1 cites·35 claims
- 4959US2017010895A1Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2016·Application pending·0 cites
- 5058US9785576B2Hardware-assisted virtualization for implementing secure video output pathINTEL CORP·Filed 2014·Granted Oct 10, 2017·1 cites·20 claims
Showing the top 50 of 80 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →