Mechanism for instruction set based thread execution on a plurality of instruction sequencers

Abstract

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

We claim: 
     
         1 . A system comprising:
 one or more processors;   an interconnect to communicatively couple at least one of the one or more processors to one or more other system components;   system memory comprising dynamic random access memory communicatively coupled to at least one of the one or more processors; and   non-volatile memory to store firmware usable during a system boot process;   wherein at least one of the one or more processors comprises:
 a plurality of simultaneous multithreading (SMT) cores to simultaneously execute a plurality of threads; 
 a first core of the plurality of SMT cores comprising:
 a first set of instruction processing resources to execute a first thread; 
 a second set of instruction processing resources to execute a second thread; and 
 thread management hardware to migrate a first thread from the first set of instruction processing resources to the second set of instruction processing resources based on characteristics of one or more instructions to be executed. 
 
   
     
     
         2 . The system as in  claim 1  wherein the thread management hardware is to migrate the first thread based on an expectation that the first thread will be executed more efficiently by the second set of instruction processing resources. 
     
     
         3 . The system as in  claim 1  further comprising:
 at least one communication device communicatively coupled to the one or more processors. 
 
     
     
         4 . The system as in  claim 1  wherein the at least one of the one or more processors is one of a plurality of processors. 
     
     
         5 . The system as in  claim 1  wherein the non-volatile memory comprises an Electrically Erasable Programmable Read-Only Memory (EEPROM). 
     
     
         6 . The system as in  claim 1  further comprising:
 cache memory communicatively coupled to the at least one of the one or more processors. 
 
     
     
         7 . A system comprising:
 instruction processing means;   interconnect means to communicatively couple the instruction processing means to one or more other system components;   memory means communicatively coupled to the instruction processing means; and   non-volatile storage means to store firmware usable during a system boot process;   wherein the instruction processing means comprises:
 simultaneous multithreading (SMT) means to simultaneously execute a plurality of threads; 
 a first of the SMT means comprising:
 first instruction processing resource means to execute a first thread; 
 second instruction processing resource means to execute a second thread; and 
 thread management means to migrate a first thread from the first instruction processing resource means to the second instruction processing resource means based on characteristics of one or more instructions to be executed. 
 
   
     
     
         8 . The system as in  claim 7  wherein the thread management means is to migrate the first thread based on an expectation that the first thread will be executed more efficiently by the second instruction processing resource means. 
     
     
         9 . The system as in  claim 7  further comprising:
 communication means communicatively coupled to the one or more processors. 
 
     
     
         10 . The system as in  claim 7  wherein the instruction processing means is one of a plurality of processors. 
     
     
         11 . The system as in  claim 7  wherein the non-volatile storage means comprises an Electrically Erasable Programmable Read-Only Memory (EEPROM). 
     
     
         12 . The system as in  claim 7  further comprising:
 cache means communicatively coupled to the at least one of the one or more processors.