Inventor · disambiguated record
Bryant Bigbee
Also filed as: BIGBEE BRYANT · BIGBEE BRYANT E
47 granted patents·8 pending applications·455 citations·filing 1997–2023
98Inventor score
Top patents by PatentIndex Score
55 records- 0197US7882339B2Primitives to enhance thread-level speculationINTEL CORP·Filed 2005·Granted Feb 1, 2011·56 cites·11 claims
- 0295US10162694B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2015·Granted Dec 25, 2018·12 cites·24 claims
- 0388US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 0487US8479217B2Apparatus, system, and method for persistent user-level threadCHINYA GAUTHAM·Filed 2011·Granted Jul 2, 2013·7 cites·19 claims
- 0587US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 0686US8301868B2System to profile and optimize user software in a managed run-time environmentNEWBURN CHRIS J·Filed 2005·Granted Oct 30, 2012·15 cites·22 claims
- 0786US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 0885US8762694B1Programmable event-driven yield mechanismZOU XIANG·Filed 2006·Granted Jun 24, 2014·24 cites·26 claims
- 0985US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 1084US7974416B2Providing a secure execution mode in a pre-boot environmentINTEL CORP·Filed 2002·Granted Jul 5, 2011·28 cites·18 claims
- 1183US11645135B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2020·Granted May 9, 2023·1 cites·27 claims
- 1283US10275598B2Providing a secure execution mode in a pre-boot environmentINTEL CORP·Filed 2015·Granted Apr 30, 2019·3 cites·12 claims
- 1380US6920581B2Method and apparatus for functional redundancy check mode recoveryINTEL CORP·Filed 2002·Granted Jul 19, 2005·29 cites·24 claims
- 1480US6349380B1Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessorINTEL CORP·Filed 1999·Granted Feb 19, 2002·91 cites·18 claims
- 1579US8516483B2Transparent support for operating system services for a sequestered sequencerCHINYA GAUTHAM·Filed 2005·Granted Aug 20, 2013·10 cites·26 claims
- 1678US7810083B2Mechanism to emulate user-level multithreading on an OS-sequestered sequencerINTEL CORP·Filed 2004·Granted Oct 5, 2010·25 cites·37 claims
- 1777US9026773B2Providing a secure execution mode in a pre-boot environmentZIMMER VINCENT J·Filed 2011·Granted May 5, 2015·3 cites·23 claims
- 1877US8522044B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Aug 27, 2013·3 cites·7 claims
- 1976US2023273846A1Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2023·Application pending·0 cites
- 2074US8028295B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2005·Granted Sep 27, 2011·4 cites·21 claims
- 2173US8719819B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2005·Granted May 6, 2014·4 cites·20 claims
- 2273US8171268B2Technique for context state management to reduce save and restore operations between a memory and a processor using in-use vectorsNEWBURN CHRIS J·Filed 2005·Granted May 1, 2012·7 cites·5 claims
- 2369US9448829B2Hetergeneous processor apparatus and methodINTEL CORP·Filed 2012·Granted Sep 20, 2016·2 cites·20 claims
- 2469US8332619B2Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2011·Granted Dec 11, 2012·2 cites·12 claims
- 2568US8887174B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersHANKINS RICHARD A·Filed 2011·Granted Nov 11, 2014·2 cites·10 claims
- 2666US8914618B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceWANG HONG·Filed 2005·Granted Dec 16, 2014·3 cites·10 claims
- 2765US10776190B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2018·Granted Sep 15, 2020·0 cites·24 claims
- 2865US9069605B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionINTEL CORP·Filed 2013·Granted Jun 30, 2015·1 cites·20 claims
- 2964US9459874B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceINTEL CORP·Filed 2014·Granted Oct 4, 2016·1 cites·18 claims
- 3064US8631261B2Context state management for processor feature setsVAN DYKE DON A·Filed 2007·Granted Jan 14, 2014·4 cites·17 claims
- 3164US7793111B1Mechanism to handle events in a machine with isolated executionINTEL CORP·Filed 2000·Granted Sep 7, 2010·7 cites·18 claims
- 3263US9588771B2Instruction set architecture-based inter-sequencer communications with a heterogeneous resourceINTEL CORP·Filed 2013·Granted Mar 7, 2017·1 cites·18 claims
- 3362US8677163B2Context state management for processor feature setsVAN DYKE DON·Filed 2013·Granted Mar 18, 2014·2 cites·11 claims
- 3461US6857066B2Apparatus and method to identify the maximum operating frequency of a processorINTEL CORP·Filed 2001·Granted Feb 15, 2005·7 cites·30 claims
- 3560US9875102B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Jan 23, 2018·0 cites·20 claims
- 3659US9766891B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 3759US2017010895A1Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2016·Application pending·0 cites
- 3857US10452403B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2015·Granted Oct 22, 2019·0 cites·16 claims
- 3957US9383997B2Apparatus, system, and method for persistent user-level threadINTEL CORP·Filed 2013·Granted Jul 5, 2016·0 cites·20 claims
- 4056US9063804B2System to profile and optimize user software in a managed run-time environmentINTEL CORP·Filed 2013·Granted Jun 23, 2015·0 cites·14 claims
- 4155US9720697B2Mechanism for instruction set based thread execution on a plurality of instruction sequencersWANG HONG·Filed 2012·Granted Aug 1, 2017·0 cites·18 claims
- 4253US8607235B2Mechanism to schedule threads on OS-sequestered sequencers without operating system interventionHANKINS RICHARD A·Filed 2004·Granted Dec 10, 2013·3 cites·34 claims
- 4352US8566567B2System to profile and optimize user software in a managed run-time environmentNEWBURN CHRIS J·Filed 2012·Granted Oct 22, 2013·0 cites·14 claims
- 4451US8671275B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Mar 11, 2014·0 cites·9 claims
- 4551US8458464B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Jun 4, 2013·0 cites·4 claims
- 4651US2013073835A1Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2012·Application pending·0 cites
- 4748US2011087867A1Primitives to enhance thread-level speculationJACOBSON QUINN A·Filed 2010·Application pending·0 cites
- 4848US2005283660A1Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2005·Application pending·0 cites
- 4945US6289431B1Method and apparatus for accessing more than 4 Gigabytes of physical memory with 4-byte table entriesINTEL CORP·Filed 1998·Granted Sep 11, 2001·17 cites·22 claims
- 5043US2004153635A1Privileged-based qualification of branch trace store dataFiled 2002·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Bryant Bigbee files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →