Hardware apparatuses and methods for memory corruption detection

Abstract

Methods and apparatuses relating to memory corruption detection are described. In one embodiment, a hardware processor includes an execution unit to execute an instruction to request access to a block of a memory through a pointer to the block of the memory, and a memory management unit to allow access to the block of the memory when a memory corruption detection value in the pointer is validated with a memory corruption detection value in the memory for the block, wherein a position of the memory corruption detection value in the pointer is selectable between a first location and a second, different location.

What is claimed is: 
     
         1 . A processor comprising:
 decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and   circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
 determine whether the first value matches a second value corresponding to the block of data; and 
 load the block of data from the memory when the first value matches the second value. 
   
     
     
         2 . The processor of  claim 1 , further comprising a configuration register to store data to indicate a number of bits of the first value. 
     
     
         3 . The processor of  claim 1 , further comprising a configuration register to store data to indicate a number of bits of the first value and to store data to indicate a position of the first value. 
     
     
         4 . The processor of  claim 1 , further comprising a configuration register to have a field to indicate which bits of the pointer are to include the first value. 
     
     
         5 . The processor of  claim 1 , further comprising a configuration register to store data to control whether the circuitry is to determine whether the first value matches the second value. 
     
     
         6 . The processor of  claim 1 , further comprising a first set of one or more configuration registers to store data to control whether the circuitry is to determine whether the first value matches the second value and to store data to indicate a number of bits of the first value. 
     
     
         7 . The processor of  claim 6 , further comprising a second set of one or more configuration registers to store data to indicate a number of bits of a third value to be included in a second pointer along with a second address. 
     
     
         8 . The processor of  claim 1 , wherein the first value does not include a most significant bit of the pointer. 
     
     
         9 . The processor of  claim 8 , wherein the most significant bit of the pointer is to have a value of one for an operating system. 
     
     
         10 . The processor of  claim 1 , wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value. 
     
     
         11 . The processor of  claim 1 , wherein the first value comprises a most significant bit of the pointer. 
     
     
         12 . The processor of  claim 1 , wherein the processor is a reduced instruction set computing (RISC) processor, and wherein the first value comprises five bits. 
     
     
         13 . The processor of  claim 12 , wherein the first value comprises ten bits. 
     
     
         14 . The processor of  claim 1 , wherein the block of data is a 128-bit block of data. 
     
     
         15 . The processor of  claim 1 , wherein the processor is to indicate if the first value does not match the second value. 
     
     
         16 . A computer system comprising:
 a dynamic random access memory (DRAM);   a processor coupled with the DRAM, the processor comprising:   decode circuitry to decode a load instruction, the load instruction to operate on a pointer, the pointer comprising an address to a block of data in memory and a first value; and   circuitry coupled with the decode circuitry, the circuitry, based on decode of the load instruction by the decode circuitry, to:
 determine whether the first value matches a second value corresponding to the block of data; and 
 load the block of data from the memory when the first value matches the second value. 
   
     
     
         17 . The computer system of  claim 16 , wherein the computer system further comprises a mass storage device coupled with the processor, and wherein the processor further comprises a configuration register to have a field to indicate which bits of the pointer are to include the first value. 
     
     
         18 . The computer system of  claim 16 , wherein the computer system further comprises a communication device coupled with the processor, and wherein the processor further comprises:
 a first set of one or more configuration registers to store data to control whether the circuitry is to determine whether the first value matches the second value and to store data to indicate a number of bits of the first value; and   a second set of one or more configuration registers to store data to indicate a number of bits of a third value to be included in a second pointer along with a second address.   
     
     
         19 . The computer system of  claim 16 , wherein the computer system further comprises a communication device coupled with the processor, wherein the first value comprises five bits, and wherein the pointer is to have a plurality of most significant canonical bits that are all to have a same value. 
     
     
         20 . A method comprising:
 decoding a load instruction, the load instruction operating on a pointer, the pointer comprising an address to a block of data in memory and a first value;   determining whether the first value matches a second value corresponding to the block of data; and   loading the block of data from the memory when the first value matches the second value.