Inventor · disambiguated record
Ron Gabor
Also filed as: GABOR RON
63 granted patents·6 pending applications·193 citations·filing 2005–2023
98Inventor score
Top patents by PatentIndex Score
69 records- 0195US10162694B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2015·Granted Dec 25, 2018·12 cites·24 claims
- 0294US9652375B2Multiple chunk support for memory corruption detection architecturesINTEL CORP·Filed 2015·Granted May 16, 2017·15 cites·20 claims
- 0394US9619313B2Memory write protection for memory corruption detection architecturesINTEL CORP·Filed 2015·Granted Apr 11, 2017·11 cites·20 claims
- 0490US9858140B2Memory corruption detectionINTEL CORP·Filed 2014·Granted Jan 2, 2018·12 cites·16 claims
- 0588US12032485B264-bit virtual addresses having metadata bit(s) and canonicality check that does not fail due to non-canonical values of metadata bit(s)INTEL CORP·Filed 2020·Granted Jul 9, 2024·2 cites·51 claims
- 0686US10725755B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsINTEL CORP·Filed 2017·Granted Jul 28, 2020·4 cites·17 claims
- 0786US10725788B1Advanced error detection for integer single instruction, multiple data (SIMD) arithmetic operationsINTEL CORP·Filed 2019·Granted Jul 28, 2020·5 cites·21 claims
- 0886US10346171B2End-to end transmission of redundant bits for physical storage location identifiers between first and second register rename storage structuresINTEL CORP·Filed 2017·Granted Jul 9, 2019·6 cites·23 claims
- 0986US8103831B2Efficient method and apparatus for employing a micro-op cache in a processorRAPPOPORT LIHU·Filed 2008·Granted Jan 24, 2012·20 cites·20 claims
- 1083US11645135B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2020·Granted May 9, 2023·1 cites·27 claims
- 1183US11288213B2Memory protection with hidden inline metadataINTEL CORP·Filed 2019·Granted Mar 29, 2022·2 cites·25 claims
- 1283US10073727B2Heap management for memory corruption detectionINTEL CORP·Filed 2015·Granted Sep 11, 2018·3 cites·20 claims
- 1383US7725745B2Power aware software pipelining for hardware acceleratorsINTEL CORP·Filed 2006·Granted May 25, 2010·12 cites·15 claims
- 1482US10095573B2Byte level granularity buffer overflow detection for memory corruption detection architecturesINTEL CORP·Filed 2017·Granted Oct 9, 2018·2 cites·20 claims
- 1581US10802567B2Performing local power gating in a processorINTEL CORP·Filed 2017·Granted Oct 13, 2020·2 cites·20 claims
- 1679US9672019B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSAGER DAVID J·Filed 2010·Granted Jun 6, 2017·6 cites·18 claims
- 1778US9229524B2Performing local power gating in a processorBONEN NADAV·Filed 2012·Granted Jan 5, 2016·3 cites·17 claims
- 1878US7827551B2Real-time threading service for partitioned multiprocessor systemsINTEL CORP·Filed 2005·Granted Nov 2, 2010·10 cites·17 claims
- 1977US12045176B2Memory protection with hidden inline metadataINTEL CORP·Filed 2023·Granted Jul 23, 2024·0 cites·21 claims
- 2077US10324857B2Linear memory address transformation and managementINTEL CORP·Filed 2017·Granted Jun 18, 2019·2 cites·22 claims
- 2177US7437546B2Multiple, cooperating operating systems (OS) platform system and methodINTEL CORP·Filed 2005·Granted Oct 14, 2008·9 cites·26 claims
- 2276US10585741B2Heap management for memory corruption detectionINTEL CORP·Filed 2018·Granted Mar 10, 2020·1 cites·17 claims
- 2376US2023273846A1Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2023·Application pending·0 cites
- 2474US11636049B2Memory protection with hidden inline metadataINTEL CORP·Filed 2022·Granted Apr 25, 2023·0 cites·20 claims
- 2573US9934164B2Memory write protection for memory corruption detection architecturesINTEL CORP·Filed 2017·Granted Apr 3, 2018·1 cites·20 claims
- 2673US8909988B2Recoverable parity and residue errorSPERBER ZEEV·Filed 2012·Granted Dec 9, 2014·3 cites·24 claims
- 2772US9003421B2Acceleration threads on idle OS-visible thread execution unitsGABOR RON·Filed 2005·Granted Apr 7, 2015·6 cites·20 claims
- 2871US9772674B2Performing local power gating in a processorINTEL CORP·Filed 2015·Granted Sep 26, 2017·1 cites·13 claims
- 2971US8782374B2Method and apparatus for inclusion of TLB entries in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Jul 15, 2014·6 cites·20 claims
- 3071US8433850B2Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Apr 30, 2013·6 cites·20 claims
- 3170US10191791B2Enhanced address space layout randomizationINTEL CORP·Filed 2016·Granted Jan 29, 2019·1 cites·25 claims
- 3270US9766968B2Byte level granularity buffer overflow detection for memory corruption detection architecturesINTEL CORP·Filed 2015·Granted Sep 19, 2017·1 cites·15 claims
- 3370US8706979B2Code reuse and locality hintingGABOR RON·Filed 2007·Granted Apr 22, 2014·5 cites·5 claims
- 3469US8543796B2Optimizing performance of instructions based on sequence detection or information associated with the instructionsFALIK OHAD·Filed 2008·Granted Sep 24, 2013·4 cites·14 claims
- 3567US8347035B2Posting weakly ordered transactionsINTEL CORP·Filed 2008·Granted Jan 1, 2013·4 cites·20 claims
- 3667US8127085B2Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processorRAPPOPORT LIHU·Filed 2008·Granted Feb 28, 2012·4 cites·16 claims
- 3765US10776190B2Hardware apparatuses and methods for memory corruption detectionINTEL CORP·Filed 2018·Granted Sep 15, 2020·0 cites·24 claims
- 3865US9690591B2System and method for fusing instructions queued during a time window defined by a delay counterOUZIEL IDO·Filed 2008·Granted Jun 27, 2017·4 cites·15 claims
- 3963US11966334B2Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bitsINTEL CORP·Filed 2021·Granted Apr 23, 2024·0 cites·24 claims
- 4063US10891230B1Apparatuses, methods, and systems for selective linear address masking based on processor privilege level and control register bitsINTEL CORP·Filed 2019·Granted Jan 12, 2021·0 cites·24 claims
- 4163US9690640B2Recovery from multiple data errorsINTEL CORP·Filed 2013·Granted Jun 27, 2017·1 cites·17 claims
- 4263US8935514B2Optimizing performance of instructions based on sequence detection or information associated with the instructionsINTEL CORP·Filed 2013·Granted Jan 13, 2015·1 cites·19 claims
- 4362US11068339B2Read from memory instructions, processors, methods, and systems, that do not take exception on defective dataINTEL CORP·Filed 2019·Granted Jul 20, 2021·0 cites·20 claims
- 4461US11030030B2Enhanced address space layout randomizationINTEL CORP·Filed 2019·Granted Jun 8, 2021·0 cites·21 claims
- 4561US8166320B2Power aware software pipelining for hardware acceleratorsGABOR RON·Filed 2010·Granted Apr 24, 2012·1 cites·21 claims
- 4660US10521361B2Memory write protection for memory corruption detection architecturesINTEL CORP·Filed 2018·Granted Dec 31, 2019·0 cites·20 claims
- 4760US9519324B2Local power gate (LPG) interfaces for power-aware operationsMISHAELI MICHAEL·Filed 2014·Granted Dec 13, 2016·1 cites·20 claims
- 4860US7650273B2Performance simulation of multiprocessor systemsINTEL CORP·Filed 2005·Granted Jan 19, 2010·2 cites·29 claims
- 4957US2017371397A1Performing Local Power Gating In A ProcessorINTEL CORP·Filed 2017·Application pending·0 cites
- 5055US11681533B2Restricted speculative execution mode to prevent observable side effectsINTEL CORP·Filed 2019·Granted Jun 20, 2023·0 cites·15 claims
Showing the top 50 of 69 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →